Patents Examined by V. N. Trans
  • Patent number: 4924430
    Abstract: The time verification scheme of the present invention operates without input stimulus to calculate delays along circuit paths including logic elements or cells from initial input to final output, or over sub-circuit paths, of a proposed logic design. The delay calculations include cell-dependent, and layout-dependent, and environmental-dependent factors to account for response delays on rising and falling signal; capacitance loading, temperature-dependency and voltage-dependency of a proposed logic design to provide output histograms and reports of information about overall performance, and timing violations of the proposed logic design with respect to operating parameters that can be selectively adjusted for manufacturing variations.
    Type: Grant
    Filed: January 28, 1988
    Date of Patent: May 8, 1990
    Assignee: Teradyne, Inc.
    Inventors: John J. Zasio, Kenneth C. Choy, Darrell R. Parham
  • Patent number: 4924394
    Abstract: An anti-skid braking system for a vehicle, having (a) hydraulic brakes for wheels of the vehicle, (b) actuators provided for respective brake groups each including at least one of the brakes, for controlling a braking pressure or pressures of the brake or brakes of the corresponding groups, (c) speed sensors, at least one of which is provided corresponding to each actuator, for detecting speeds of the wheels, and (d) to controller operable for: normally presuming that an actual speed of the vehicle is represented by a highest one of the detected wheel speeds; after a deceleration value of the highest speed has exceeded a preset upper limit, fixing the deceleration value of the vehicle at the preset upper limit, and presuming the actual vehicle speed based on the upper limit; and calculating a slip amount of each wheel based on a difference between the presumed vehicle speed and the detected wheel speed, to control each actuator so as to prevent the wheel from skidding.
    Type: Grant
    Filed: June 26, 1989
    Date of Patent: May 8, 1990
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Kiyoyuki Uchida, Hideo Inoue, Tatsuo Sugitani
  • Patent number: 4922425
    Abstract: A self-diagnostic method for controlling an AMT system (10) is provided including sensing and identifying faulty input signals (THD, THPS and RTDS) from the throttle position sensor assembly (22) sensors (22A, 22B and 22C). If only a known one of the input signals is faulty, logic method of control (38) is modified to a logic method tolerant of the identified faulty input signal.
    Type: Grant
    Filed: November 2, 1987
    Date of Patent: May 1, 1990
    Assignee: Eaton Corporation
    Inventors: William J. Mack, William F. Cote
  • Patent number: 4922429
    Abstract: A method for feedback controlling an air/fuel ratio of mixture supplied to an internal combustion engine to a target air/fuel ratio, which uses an output signal of an oxygen concentration sensor. The sensor's output signal is proportional to the oxygen concentration in the exhaust gas of the engine. When the target air/fuel ratio is set at a stoichiometric air/fuel ratio, the air/fuel ratio of the mixture is varied by a small amount around the stoichiometric value if the air/fuel ratio of mixture supplied to the engine is detected to be in a predetermined air/fuel ratio range which includes the stoichiometric air/fuel ratio. The determination of the air/fuel ratio is calculated from the output signal of the oxygen concentration sensor.
    Type: Grant
    Filed: March 3, 1987
    Date of Patent: May 1, 1990
    Assignee: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Toyohei Nakajima, Yasushi Okada, Toshiyuki Mieno, Nobuyuki Oono
  • Patent number: 4922441
    Abstract: A gate array device includes a plurality of basic cell regions spaced apart from one another to thereby define a plurality of intermediate regions therebetween. Each intermediate region may serve either as a memory or function cell region or as an interconnection region at least partly. The memory cell region may be selectively defined as a ROM or a RAM by metallization. A test mode or a normal operating mode may be set selectively in accordance with a control signal. When the normal operating mode is set, an input terminal is operatively connected to a memory circuit through a logic circuit; whereas, when the test mode is set, the input terminal is directly connected to the memory circuit while bypassing the logic circuit. Also provided is a memory cell structure which can be defined as a RAM memory cell or as a ROM memory cell storing a selected binary data by metallization.
    Type: Grant
    Filed: January 14, 1988
    Date of Patent: May 1, 1990
    Assignee: Ricoh Company, Ltd.
    Inventors: Toshihiro Tsukagoshi, Masanobu Fukushima, Keiichi Yoshioka, Takashi Yasui
  • Patent number: 4922430
    Abstract: A method is provided for controlling the movement of an object 1, 61, in an environment 64. The method involves making predictions of collisions, given the outlines of the object and the environment, so that avoiding action can be taken. The object and environment are modelled as clusters of interpenetrating spherical bubbles, the model comprising the relative positions of the centers 6, 7, 8, 9, and 21 to 28 inclusive of the bubbles and their respective radii. The model simplifies the prediction of the point of collision of two such modelled objects by examining the collisions between bubbles only. An early, safe, approximate prediction of the collision can be obtained using Newton's approximation.
    Type: Grant
    Filed: October 30, 1987
    Date of Patent: May 1, 1990
    Assignee: U.S. Philips Corporation
    Inventor: Peter R. Wavish
  • Patent number: 4922432
    Abstract: The present invention provides a computer-aided design system and method for designing an application specific integrated circuit which enables a user to define functional architecture independent specifications for the integrated circuit and which translates the functional architecture independent specifications into the detailed information needed for directly producing the integrated circuit. The functional architecture independent specifications of the desired integrated circuit can be defined at the functional architecture independent level in a flowchart format. From the flowchart, the system and method uses artificial intelligence and expert systems technology to generate a system controller, to select the necessary integrated circuit hardware cells needed to achieve the functional specifications, and to generate data and control paths for operation of the integrated circuit. This list of hardware cells and their interconnection requirements is set forth in a netlist.
    Type: Grant
    Filed: January 13, 1988
    Date of Patent: May 1, 1990
    Assignees: International Chip Corporation, Ricoh Company, Ltd.
    Inventors: Hideaki Kobayashi, Masahiro Shindo
  • Patent number: 4918616
    Abstract: A tool monitoring system for detecting a tool failure of a tool employed in a tool machine, comprising artificial signal generating unit for generating a predetermined artificial tool failure signal simulating the acoustic emission signal obtained in an actual failure of the tool, acoustic emission transducing unit adapted to be mounted on the tool machine near the tool and driven by the artificial signal generating unit for applying the artificial tool failure signal to the tool machine, acoustic emission sensing unit mounted on the tool machine near the tool so as to receive, in a setting mode of the system where the transducing unit is mounted on the machine, the applied artificial tool failure signal from the acoustic emission transducing unit through the tool machine and, in a monitoring mode of the system where the tool is operated, an acoustic emission from the tool, and signal processing unit for analyzing an output signal generated from the acoustic emission sensing unit to detect the tool failure of
    Type: Grant
    Filed: May 16, 1985
    Date of Patent: April 17, 1990
    Assignee: Omron Tateisi Electronics Co.
    Inventors: Kiyokazu Yoshimura, Norio Miyawaki, Hiroyuki Yamada, Hideaki Nakamura, Koichi Tshujino, Takaharu Takinami, Tatemitsu Hirayama, Tatsuhiko Naito, Ryoichi Miyake, Takeshi Yamada, Tetsuro Iwakiri, Kazuaki Otsuka
  • Patent number: 4916632
    Abstract: A vibration control apparatus detects a physical value influencing characteristics of a suspension supporting a vibrating body and a state value representing movement of the suspension, calculates an optimal target control force in consideration of an external force or disturbance acting on the suspension on the basis of the physical and state values as outputs from a state detecting system, calculates the detection control force corresponding to the detected physical value, and continuously variably controls the suspension characteristics so as to generate a control force corresponding to the difference between the target and detection control forces in consideration of the external force or disturbance acting on the suspension, whereby vibrations are prevented by equivalently applying the target control force on the suspension.
    Type: Grant
    Filed: November 3, 1986
    Date of Patent: April 10, 1990
    Assignee: Kabushiki Kaisha Toyota Chuo Kenkyusho
    Inventors: Shunichi Doi, Eiichi Yasuda, Yasutaka Hayashi
  • Patent number: 4916627
    Abstract: An apparatus and method for reducing the number of gate levels of a logic network. The gates of the network are levelized in a forward and backward direction to determine the worst path length of the network. A gate in the worst path is selected in accordance with a specified scoring function. A local Boolean compression is applied to the selected gate, thereby reducing the number of gate levels of the logic network.
    Type: Grant
    Filed: December 2, 1987
    Date of Patent: April 10, 1990
    Assignee: International Business Machines Corporation
    Inventor: David J. Hathaway
  • Patent number: 4916629
    Abstract: The invention is a method of assisting lumber grading using an electro-optical scanning system. A first critical determination is determination of pith position of the log from which the lumber was cut, relative to the scanned faces. This then indicates knot orientation. With knot orientation known, knot size and position data also determined by the scanning system can be used to accurately estimate cross sectional area of the knots. From this point a tentative lumber grade can readily be assigned. Pith position is indicated by a number of factors including wane, knot counts on each of the faces and the presence or absences of spiky faces. A preferred form the scanner is one which measures localized wood fiber angles relative to three orthogonal axes. These fiber angle measurements reveal grain slope disturbances on the lumber which are indicative of many types of defects including knots. The system has been used for grading lumber at speeds as high as 350 m/min. with considerable accuracy.
    Type: Grant
    Filed: May 31, 1988
    Date of Patent: April 10, 1990
    Assignee: Weyerhaeuser Company
    Inventors: David N. Bogue, Charles F. Horn, Steven L. Washburn, Stanley L. Floyd
  • Patent number: 4910680
    Abstract: There is disclosed a computer-aided automatic wiring method for a semi-custom logic LSI having input/output circuit blocks arranged in the peripheral portion of a chip substrate and function blocks arranged in a substrate surface region surrounded by the input/output circuit blocks and selected to provide a desired logic function. Channels functioning as wiring regions are defined around the function blocks to include internal channels positioned between the function blocks and peripheral channels arranged in direct contact with the input/output circuit blocks. The internal channels are sequentially subjected to the wiring process according to the limitation of a predetermined processing order. After the wiring process for the internal channels is completed, the peripheral channels are merged to form a square ring-form channel region. Then, the square ring-form channel region is unidimensionally developed to form a belt-like channel region.
    Type: Grant
    Filed: March 25, 1988
    Date of Patent: March 20, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tamotsu Hiwatashi
  • Patent number: 4910679
    Abstract: An exposure apparatus usable in the manufacture of semiconductor devices, for transferring a pattern of a reticle onto each of discrete areas of a semiconductor wafer in a step-and-repeat manner. The apparatus has a laser interferometer for precisely measuring the amount of displacement of the wafer and a memory for storing positional errors of the shot areas, relative to respective target positions, established at the time of completion of the stepwise movements of the wafer. In accordance with the stored positional errors and with the result of measurement by the laser interferometer, the amount of stepwise movement of the wafer is corrected, whereby the accuracy of step-feed for the wafer is improved without decreasing the throughput. In another aspect, the exposure apparatus is provided with a TTL detection system for detecting the positional error of each of the shot areas relative to a target or reference shot area established at the time of completion of stepwise movement of the wafer.
    Type: Grant
    Filed: April 13, 1989
    Date of Patent: March 20, 1990
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazuo Takahashi, Masao Kosugi
  • Patent number: 4908772
    Abstract: An integrated circuit, and a method for laying out and creating the integrated circuit, which contains large circuit blocks placed at any desired location on a chip, with the rest of the circuitry placed in the remaining non-rectangular area on the chip. The layout takes account of connections from within the circuit area to connection points external to the area. The procedure for the automatic layout proceeds in two steps. The first step is global partitioning and placement, and the second is detailed placement. The global partitioning performs the logical partitioning of the cells into clusters to be placed among and between the macro cells and the external terminals, with each cluster being eventually laid-out in a rectangular area. The second step involves the detailed placement of cells within the rectangular areas. Partitioning is accomplished by an iterative process, where at each iterative step the non-rectangular area is divided into two parts of approximately equal size.
    Type: Grant
    Filed: March 30, 1987
    Date of Patent: March 13, 1990
    Assignee: Bell Telephone Laboratories
    Inventor: Mely C. Chi
  • Patent number: 4908771
    Abstract: In order to adaptively determine the original pulse widths of individual pulses of the pulse signal, there are measured the pulse widths of the distorted pulses. A predetermined number of threshold values is preset for such measured pulse widths. The preset threshold values define classes of pulse widths intended to contain pulse widths of pulses which originally had the same pulse widths. The matching between the measured pulse widths and the preset threshold values is improved by means of a statistical evaluation of the measured pulse widths. The apparatus for carrying out the aforementioned method comprises a unit or circuit for measuring the pulse widths of the individual pulses, a unit or circuit for statistically evaluating the measured pulse widths and a unit or circuit for processing the measured pulse widths.
    Type: Grant
    Filed: July 6, 1987
    Date of Patent: March 13, 1990
    Assignee: Willi Studer AG
    Inventor: Julien Piot
  • Patent number: 4907165
    Abstract: The method of measuring an electric energy supplied to a load comprises sampling the value of a load voltage or current a desired number of times, converting each of the sampled analog values to a digital value by an A/D converter, accumulating the digital values obtained correspondingly to the number of times of such sampling actions, dividing the accumulated value by the said number to calculate an average value per sampling, and correcting the offset in the A/D converter by the average value thus obtained.
    Type: Grant
    Filed: March 13, 1989
    Date of Patent: March 6, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Masayoshi Toda
  • Patent number: 4901259
    Abstract: Disclosed is a simulation model which facilitates the "real-time" simulation of application specific integrated circuits (ASICs) in the actual digital computer system in which they will be incorporated. Significantly, this invention permits the emulation of an ASIC device, and thus does not require the fabrication of an actual physical specimen of that device. Instead, this invention permits the use of a software model which facilitates debugging of the ASIC device and permits effective generation of system test vectors. Such an approach facilitates the system-level testing of ASIC devices prior to fabrication, by permitting both the generation of system test vectors and the debugging of the internal behavior of such ASIC devices without limiting the flexibility, with respect to other devices in the system, of either simulating such devices in software or utilizing actual physical specimens of such devices.
    Type: Grant
    Filed: August 15, 1988
    Date of Patent: February 13, 1990
    Assignee: LSI Logic Corporation
    Inventor: Daniel R. Watkins
  • Patent number: 4899280
    Abstract: An adaptive control system for categorized engine conditions is disclosed in which the engine conditions to be controlled are discriminated and classified in accordance with the driver's intent and the vehicle operating conditions. It is decided that a given engine control condition is continued or the transition is under way between different control conditions as a history judgement, and a vehicle operation parameter is determined in accordance with the determined history. At the same time, in accordance with the control condition decided and classified, an operating signal is applied to the engine with an operating parameter thus determined and the result of engine control response is observed to update the adaptive parameter.
    Type: Grant
    Filed: April 8, 1988
    Date of Patent: February 6, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Mikihiko Onari, Teruji Sekozawa, Motohisa Funabashi
  • Patent number: 4897795
    Abstract: A digital image analysis system is disclosed in which a digital input image formed by a raster scan method is so modified as to fill up a hole in a clump and a recess at the bottom of a clump viewed in the sub-scanning direction of the raster scan method, for the purpose of forming a control image, the state of a clump at two consecutive scanning lines of the control image (that is, the generation and termination of the clump at one of the scanning lines or the continuity of the clump at the scanning lines) is detected from the values of adjacent pixels on the two consecutive scanning lines, and a feature value of the clump is calculated on the basis of the detected state of the clump.
    Type: Grant
    Filed: February 16, 1988
    Date of Patent: January 30, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Haruo Yoda, Hidenori Inouchi, Hiroshi Sakou, Yozo Ohuchi
  • Patent number: 4897791
    Abstract: An asynchronous fuel injection control method for engines where the amount of increase of air sucked into the cylinder of the engine corresponding to the variation of the throttle angle is estimated on the basis of a physical model formula expressing the amount of the sucked air in the cylinder, and a pulse width according to which the fuel is injected by the asynchronous injection into the engine is determined on the basis of the estimated amount of increase of the sucked air.
    Type: Grant
    Filed: August 18, 1986
    Date of Patent: January 30, 1990
    Assignee: Hitachi, Ltd.
    Inventors: Teruji Sekozawa, Makoto Shioya, Motohisa Funabashi