Abstract: A method is disclosed for removing liquids from a semiconductor substrate by contacting the liquid on the substrate with a liquid which attracts the liquid on the substrate, separating the liquids from the substrate, and inducing a phase transition in a layer on the substrate. In particular, the method is applicable to removing water from a water-containing layer on the substrate by contacting the layer with a hygroscopic liquid. Trenches on a substrate can be isolated by filling the trenches with a water-containing gel formed by reacting silane and hydrogen peroxide. The gel is contacted with sulfuric acid to remove a portion of the water from the gel before annealing to form silica in the trenches. Unlike filled trenches formed by conventional technology, there are no voids in the bottom of the trenches. The method is also applicable to forming dielectric layers which cover metal lines, low-dielectric layers, and interlayer dielectric layers.

Abstract: An electrode manufacturing method comprises: forming plural protruding portions on a surface of a substrate; introducing first particles having a size that changes according to heat, light, or a first solvent between said plural protruding portions; changing the size of the first particles by applying heat, light, or the first solvent to said first particles; and depositing an electrode material onto the surface of said substrate.

Abstract: A chalcogenide comprising material is formed to a first thickness over the first conductive electrode material. The chalcogenide material comprises AxBy. A metal comprising layer is formed to a second thickness over the chalcogenide material. The metal comprising layer defines some metal comprising layer transition thickness for the first thickness of the chalcogenide comprising material such that when said transition thickness is met or exceeded, said metal comprising layer when diffused within said chalcogenide comprising material transforms said chalcogenide comprising material from an amorphous state to a crystalline state. The second thickness being less than but not within 10% of said transition thickness. The metal is irradiated effective to break a chalcogenide bond of the chalcogenide material at an interface of the metal and chalcogenide material and diffuse at least some of the metal into the chalcogenide material.

Abstract: A gallium nitride-based III-V Group compound semiconductor device has a gallium nitride-based III-V Group compound semiconductor layer provided over a substrate, and an ohmic electrode provided in contact with the semiconductor layer. The ohmic electrode is formed of a metallic material, and has been annealed.

Abstract: A metal-containing semiconductor layer having a high dielectric constant is formed with a method that avoids inclusion of contaminant elements that reduce dielectric constant of metals. The metal-containing semiconductor layer is formed overlying a substrate in a chamber. A precursor is introduced to deposit at least a portion of the metal-containing semiconductor layer. The precursor contains one or more elements that, if allowed to deposit in the metal-containing layer, would become impurity elements. A reactant gas is used to purify the metal-containing layer by removing impurity elements from the metal-containing layer which were introduced into the chamber by the precursor.

Abstract: A method of judging a residual film on a sample by an optical measurement, the sample including a first metal film whose reflectance is changed depending on a wavelength of measuring light, and an insulating film formed above the first metal film, and the residual film being a second metal film above the insulating film, the method comprising irradiating the sample with a measuring light so as to measure a change in intensity of light reflected from the sample depending on the wavelength of the measuring light, thereby obtaining a reflectance spectrum curve, and dividing the reflectance spectrum curve into a plurality of wavelength regions so as to judge presence or absence of the second metal film above the insulating film depending on a waveform in each of the wavelength regions of the reflectance spectrum curve.

Abstract: A method for forming a strained silicon layer device with improved wafer throughput and low defect density including providing a silicon substrate; epitaxially growing a first silicon layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; epitaxially growing a step-grade SiGe buffer layer over and contacting the first silicon layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; epitaxially growing a SiGe capping layer over and contacting the step-grade SiGe buffer layer using at least one deposition precursor selected from the group consisting of disilane and trisilane; and, epitaxially growing a second silicon layer using at least one deposition precursor selected from the group consisting of disilane and silane.

Abstract: A process for manufacturing a substrate with an embedded capacitor is disclosed. A first metal wiring layer including a lower electrode pad is formed on a substrate base. A dielectric layer is formed a on the substrate base by build-up coating. A hole is formed in the dielectric layer to expose the lower electrode pad, then a medium material is filled into the hole. The medium material is ground to have a ground surface coplanar to the dielectric layer. A second metal wiring layer including an upper electrode pad is formed on dielectric layer, the upper electrode pad covers the ground surface of the medium material and is parallel to the lower electrode pad so as to form an embedded capacitor.

Abstract: Disclosed is a method of forming a capacitor of a semiconductor device which can secure a desired leakage current characteristic while securing a desired charging capacitance. The inventive method of forming a capacitor of a semiconductor device comprises steps of: forming a bottom electrode on a semiconductor substrate with a storage node contact so that the bottom electrode is connected with the storage node contact; plasma-nitrifying the bottom electrode to form a first nitrification film on the surface of the bottom electrode; forming a La2O3 dielectric film on the bottom electrode including the first nitrification film; plasma-nitrifying the La2O3 dielectric film to form a second nitrification film on the surface of the La2O3 dielectric film; and forming a top electrode on the La2O3 dielectric film including the second nitrification film.

Abstract: The invention encompasses a method of forming a silicon nitride layer. A substrate is provided which comprises a first mass and a second mass. The first mass comprises silicon and the second mass comprises silicon oxide. A sacrificial layer is formed over the first mass. While the sacrificial layer is over the first mass, a nitrogen-containing material is formed across the second mass. After the nitrogen-containing material is formed, the sacrificial layer is removed. Subsequently, a silicon nitride layer is formed to extend across the first and second masses, with the silicon nitride layer being over the nitrogen-containing material. Also, a conductivity-enhancing dopant is provided within the first mass. The invention also pertains to methods of forming capacitor constructions.

Abstract: Metal CMP slurry compositions having relatively low chemical etch rate and relatively high mechanical polishing rate characteristics are provided. The relatively high mechanical polishing rate characteristics are achieved using relatively high concentrations of mechanical abrasive (e.g., ?8 wt %) in combination with sufficient quantities of a wetting agent to inhibit micro-scratching of underlying surfaces (e.g., insulating layers, conductive vias, . . . ) being polished. The slurry compositions also include a highly stable metal-propylenediaminetetraacetate (M-PDTA) complex, which may operate to inhibit metal-oxide re-adhesion on the metal surface being polished and/or inhibit oxidation of the metal surface by chelating with the surface.

Abstract: The present invention generally provides a process for depositing silicon carbide using a silane-based material with certain process parameters that is useful for forming a suitable ARC for IC applications. Under certain process parameters, a fixed thickness of the silicon carbide may be used on a variety of thicknesses of underlying layers. The thickness of the silicon carbide ARC is substantially independent of the thickness of the underlying layer for a given reflectivity, in contrast to the typical need for adjustments in the ARC thickness for each underlying layer thickness to obtain a given reflectivity. Another aspect of the invention includes a substrate having a silicon carbide anti-reflective coating, comprising a dielectric layer deposited on the substrate and a silicon carbide anti-reflective coating having a dielectric constant of less than about 7.0 and preferably about 6.0 or less.

Abstract: A novel method for depositing a barrier layer on a single damascene, dual damascene or other contact opening structure. The method eliminates the need for pre-cleaning argon ion bombardment of the structure, thereby reducing or eliminating damage to the surface of the underlying conductive layer and sputtering of copper particles to the via or other contact opening sidewall. The process includes fabrication of a single damascene, dual damascene or other contact opening structure on a substrate; optionally pre-cleaning the structure typically using nitrogen or hydrogen plasma; depositing a thin metal barrier layer on the sidewalls and bottom of the structure; and redistributing or re-sputtering the barrier layer on the bottom and sidewalls of the structure.

Abstract: Disclosed is a method for depositing a silicon nitride layer of a semiconductor device. The method includes the steps of providing Al-based compound as a catalyst, and reacting DCS with NH3 by using the Al catalyst, thereby depositing the silicon nitride layer. DCS is reacted with NH3 by using the Al catalyst when depositing the silicon nitride layer, so dissolution of DCS is promoted by means of the Al catalyst, so that the silicon nitride layer is deposited at a high speed, thereby improving productivity of semiconductor devices. The silicon nitride layer is deposited by using DCS under a low-temperature condition of about 500 to 800° C., without deteriorating device characteristics.

Abstract: A method for providing gates of transistors with at least two different work functions utilizes a silicidation of two different metals at different times, silicidation for one gate and polysilicon for the other, or silicidation using a single metal with two differently doped silicon structures. Thus the problem associated with performing silicidation of two different metals at the same time is avoided. If the two metals have significantly different silicidation temperatures, the one with the lower temperature silicidation will likely have significantly degraded performance as a result of having to also experience the higher temperature required to achieve silicidation with the other metal.

Abstract: This invention is to guarantee that in separating a plate member such as a bonded substrate stack, a fluid is injected to an appropriate portion of the plate member. While a bonded substrate stack (50) is rotated, the vertical position of its peripheral portion is measured throughout its perimeter by a measuring device (150). Then, while the vertical position of a nozzle (120) is dynamically adjusted on the basis of the measurement result, and at the same time, the bonded substrate stack (50) is rotated, the bonded substrate stack (50) is separated into two substrates at a porous layer by injecting a fluid ejected from the nozzle (120).

Abstract: A method of manufacturing a gallium nitride (GaN)-based semiconductor light emitting device includes forming a contact resistance improved layer on a p-type GaN-based semiconductor layer with at least one metal selected from the group of Au, Mg, Mn, Mo, Pd, Pt, Sn, Ti and Zn, heat-treating the p-type GaN-based semiconductor layer so that elements in the contact resistance improved layer diffuse into the p-type GaN-based semiconductor layer and that Ga elements in the p-type GaN-based semiconductor layer dissolve into the contact resistance improved layer, and removing the contact resistance improved layer remaining on the p-type GaN-based semiconductor layer.

Abstract: An organic polymer film of low dielectric constant and high heating resistance which is applicable as an insulating layer of a semiconductor devices is provided, as well as a manufacturing method for the film and a semiconductor device incorporating the film.

Abstract: A method of rapid etching of an insulating film including an organic-based dielectric film without forming a damage layer or causing decline of the throughput, including the steps of forming an insulating film including an organic-based dielectric film such as a stacked film comprised of a polyarylether film or other organic-based dielectric film and a silicon oxide-based dielectric film or other insulating film, forming a mask layer by patterning above the insulating film, and when etching the organic-based dielectric film portion, using ions or radicals containing NH group generated by gaseous discharge in a mixed gas of hydrogen gas and nitrogen gas or a mixed gas of ammonia gas for etching using the mask layer as an etching mask, to etch the insulating layer and form openings etc. while generating reaction products containing CN group.

Abstract: A no-flow underfill material and process suitable for underfilling a bumped circuit component. The underfill material initially comprises a dielectric polymer material in which is dispersed a precursor capable of reacting to form an inorganic filler. The underfill process generally entails dispensing the underfill material over terminals on a substrate, and then placing the component on the substrate so that the underfill material is penetrated by the bumps on the component and the bumps contact the terminals on the substrate. The bumps are then reflowed to form solid electrical interconnects that are encapsulated by the resulting underfill layer. The precursor may be reacted to form the inorganic filler either during or after reflow.