Patents Examined by Valerie N Newton
  • Patent number: 10896946
    Abstract: An organic light emitting diode display device includes a substrate, light emitting structures, fan-out wirings, and a wiring structure. The substrate has a display region including a light emitting region and a peripheral region surrounding the light emitting region and a pad region located in one side of the display region. The light emitting structures are disposed in the light emitting region on the substrate. The fan-out wirings are disposed in the peripheral region on the substrate, and the fan-out wirings include a straight-line portion and an oblique line portion. The wiring structure is disposed on the fan-out wirings, and includes a conductive layer and conductive patterns spaced apart from each other and disposed on the conductive layer.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: January 19, 2021
    Inventors: Jisu Na, Kwang-Min Kim, Ki Wook Kim, Hyun Joon Kim
  • Patent number: 10897009
    Abstract: Resistive memory cells, precursors thereof, and methods of making resistive memory cells are described. In some embodiments, the resistive memory cells are formed from a resistive memory precursor that includes a switching layer precursor containing a plurality of oxygen vacancies that are present in a controlled distribution therein, optionally without the use of an oxygen exchange layer. In these or other embodiments, the resistive memory precursors described may include a second electrode formed on a switching layer precursor, wherein the second electrode is includes a second electrode material that is conductive but which does not substantially react with oxygen. Devices including resistive memory cells are also described.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: January 19, 2021
    Assignee: Intel Corporation
    Inventors: Niloy Mukherjee, Ravi Pillarisetty, Prashant Majhi, Uday Shah, Ryan E Arch, Markus Kuhn, Justin S. Brockman, Huiying Liu, Elijah V Karpov, Kaan Oguz, Brian S. Doyle, Robert S. Chau
  • Patent number: 10886285
    Abstract: A method of forming memory circuitry comprises using a digitline mask to form both: (a) conductive digitlines in a memory array area, and (b) lower portions of conductive vias in a peripheral circuitry area laterally of the memory array area. The lower portions of the vias electrically couple with circuitry below the vias and the digitlines. Pairs of conductive wordlines are formed above the digitlines in the memory array area. The pairs of wordlines extend from the memory array area into the peripheral circuitry area. Individual of the pairs are directly above individual of the lower portions of individual of the vias. Individual upper portions of the individual vias are formed. The individual upper portions both: (c) directly electrically couple to one of the individual lower portions of the individual vias, and (d) directly electrically couple together the wordlines of the individual pair of wordlines that are directly above the respective one individual lower portion of the respective individual via.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: January 5, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 10886444
    Abstract: A wafer-level process for manufacturing solid state lighting (“SSL”) devices using large-diameter preformed metal substrates is disclosed. A light emitting structure is formed on a growth substrate, and a preformed metal substrate is bonded to the light emitting structure opposite the growth substrate. The preformed metal substrate can be bonded to the light emitting structure via a metal-metal bond, such as a copper-copper bond, or with an inter-metallic compound bond.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: January 5, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Vladimir Odnoblyudov
  • Patent number: 10886211
    Abstract: A wiring board includes: a Cu pad; an insulating layer covering the Cu pad and having an opening portion; a first metallic layer formed on the Cu pad in the opening portion; and a connecting terminal formed on the first metallic layer to extend from the opening portion to above an upper surface of the insulating layer. The connecting terminal includes: a seed layer formed on the first metallic layer; and a second metallic layer formed on the seed layer. A stacked body is formed of the first metallic layer and the connecting terminal and includes a constricted portion. The constricted portion is located in a certain position of the first metallic layer in a thickness direction of the first metallic layer, and a sectional area of the stacked body is the smallest at the constricted portion.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: January 5, 2021
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Yasuyuki Yamaguchi
  • Patent number: 10879468
    Abstract: To provide a layer such as a charge transport layer having a refractive index significantly lowered without impairing electrical conductivity and surface roughness, and a method for producing it. A deposited film composition obtained by co-depositing a fluorinated polymer having a saturated vapor pressure at 300° C. of at least 0.001 Pa and an organic semiconductor material.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: December 29, 2020
    Assignees: National University Corporation Yamagata University, AGC Inc.
    Inventors: Daisuke Yokoyama, Takefumi Abe, Yasuhiro Kuwana
  • Patent number: 10879446
    Abstract: Embodiments of the present disclosure relate to quantum circuit assemblies implementing superconducting qubits, e.g., transmons, in which SQUID loops and portions of FBLs configured to magnetically couple to the SQUID loops extend substantially vertically. In contrast to conventional implementations, for a vertical SQUID according to various embodiments of the present disclosure, a line that is perpendicular to the SQUID loop is parallel to the qubit substrate. A corresponding FBL is also provided in a vertical arrangement, in order to achieve efficient magnetic coupling to the vertical SQUID loop, by ensuring that at least a portion of the FBL designed to conduct current responsible for generating magnetic field for tuning qubit frequency is substantially perpendicular to the substrate.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: December 29, 2020
    Assignee: Intel Corporation
    Inventors: Roman Caudillo, Lester Lampert, David J. Michalak, Jeanette M. Roberts, Ravi Pillarisetty, Hubert C. George, Nicole K. Thomas, James S. Clarke
  • Patent number: 10871415
    Abstract: Systems and methods are disclosed for packaging sensors for use in high temperature environments. In one example implementation, a sensor device includes a header; one or more feedthrough pins extending through the header; and a sensor chip disposed on a support portion of the header. The sensor chip includes one or more contact pads. The sensor device further includes one or more wire bonded interconnections in electrical communication with the respective one or more contact pads and the respective one or more feedthrough pins. The sensor device includes a first sealed enclosure formed by at least a portion of the header. The first sealed enclosure is configured for enclosing and protecting at last the one or more wire bonded interconnections and the one or more contact pads from an external environment.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: December 22, 2020
    Assignee: Kulite Semiconductor Products, Inc.
    Inventors: Alexander A. Ned, Leo Geras, Sorin Stefanescu
  • Patent number: 10868131
    Abstract: A method for forming a gaseous spacer in a semiconductor device and a semiconductor device including the gaseous spacer are disclosed. In an embodiment, the method may include forming a gate stack over a substrate, depositing a first gate spacer on sidewalls of the gate stack, epitaxially growing source/drain regions on opposite sides of the gate stack, and depositing a second gate spacer over the first gate spacer to form a gaseous spacer below the second gate spacer. The gaseous spacer may be disposed laterally between the source/drain regions and the gate stack.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Hao Yeh, Ching Yu Huang
  • Patent number: 10854744
    Abstract: A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 ?m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: December 1, 2020
    Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
    Inventors: Yoshihiro Matsushima, Shigetoshi Sota, Eiji Yasuda, Toshikazu Imai, Ryosuke Okawa, Kazuma Yoshida, Ryou Kato
  • Patent number: 10854529
    Abstract: A high resistivity wafer with a heat dissipation structure includes a high resistivity wafer and a metal structure. The high resistivity wafer includes a heat dissipation region and a device support region. The high resistivity wafer consists of an insulating material. The metal structure is only embedded within the heat dissipation region of the high resistivity wafer. The metal structure surrounds the device support region.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: December 1, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Kuo-Yuh Yang, Chia-Huei Lin
  • Patent number: 10847674
    Abstract: A light emitting device includes: a substrate; a first electrode and a second electrode provided at a distance from each other on the substrate and extending in one direction; a plurality of light emitting diodes provided between the first electrode and the second electrode, and connected to the first electrode and the second electrode; and a residual pattern provided between at least one of the plurality of light emitting diodes and the substrate.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: November 24, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yeoung Keol Woo, Chul Min Bae
  • Patent number: 10840139
    Abstract: A semiconductor device includes a fin type pattern extending in a first direction on a substrate, a field insulating layer on the substrate, the field insulating layer wrapping a side wall of the fin type pattern, a gate electrode on the fin type pattern, the gate electrode extending in a second direction intersecting with the first direction, a first spacer on a side wall of a lower part of the gate electrode, and an etching stop layer extending along a side wall and an upper surface of an upper part of the gate electrode, along a side wall of the first spacer, and along an upper surface of the field insulating layer.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: November 17, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Geum Jung Seong, Seung Soo Hong, Young Mook Oh, Jeong Yun Lee
  • Patent number: 10840443
    Abstract: A three-dimensional variable resistance memory array and method of forming the same. The memory array has memory cells in multiple planes in three dimensions. The planes of the memory cells include shared interconnect lines, dually connected to driving and sensing circuits, that are used for addressing the cells for programming and reading. The memory array is formed using only a single patterned mask per central array plane to form the memory cells of such planes.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventor: David H. Wells
  • Patent number: 10840315
    Abstract: A display substrate includes: a pixel-defining layer located on the display substrate and including a plurality of light-emitting regions; and a plurality of light-emitting devices located in the plurality of light-emitting regions, respectively, wherein each of the plurality of light-emitting devices includes a pixel electrode, a common electrode, and an organic light-emitting portion between the pixel electrode and the common electrode, wherein the pixel-defining layer includes a first inner side surface and a second inner side surface facing each other in each of the plurality of light-emitting regions, and the pixel electrode is on the first inner side surface and the common electrode is on the second inner side surface.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: November 17, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventor: Hyunwoo Lee
  • Patent number: 10833186
    Abstract: A method for making a multilayered device on an engineered substrate having a substrate coefficient of thermal expansion includes growing a buffer layer on the engineered substrate, and growing a first epitaxial layer on the buffer layer. The first epitaxial layer is characterized by an epitaxial coefficient of thermal expansion substantially equal to the substrate coefficient of thermal expansion.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: November 10, 2020
    Assignee: Qromis, Inc.
    Inventors: Vladimir Odnoblyudov, Steve Lester, Ozgur Aktas
  • Patent number: 10825733
    Abstract: Multiple wide bandgap semiconductor wafers, each having active circuitry and an epitaxially formed backside drain contact layer, may be constructed from a single bulk semiconductor substrate by: forming foundational layers on the top of the bulk substrate via epitaxy; forming active circuitry atop the foundational layers; laser treating the backside of the bulk substrate to create a cleave line in one of the foundational layers; and exfoliating a semiconductor wafer from the bulk substrate, where the exfoliated semiconductor wafer contains the active circuits and at least a portion of the foundational layers. Wafers containing the foundational layers without complete active devices may be produced in a similar manner. The foundational layers may comprise a drain contact layer and a drift layer, and may additionally include a buffer layer between the drain contact layer and the drift layer.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: November 3, 2020
    Assignee: United Silicon Carbide, Inc.
    Inventors: Anup Bhalla, Leonid Fursin
  • Patent number: 10818606
    Abstract: An alignment mark pattern is provided. The alignment mark pattern includes a first region that includes a first line and a first space having different widths therebetween, a second region that includes a second line and a second space having different widths therebetween, a third region that includes a third line and a third space having different widths therebetween, and a fourth region that includes a fourth line and a fourth space having different widths therebetween. The first and second lines extend in a first direction. The third and fourth lines extend in a second direction perpendicular to the first direction. The first region is diagonal to the second region. The third region is diagonal to the fourth region. The third region is adjacent to the first and second regions. The fourth region is adjacent to the first and second regions.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: October 27, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Jun-Che Wu, Jing-Hua Chiang, Wen-Keir Liang, Ming-Yu Chen
  • Patent number: 10804130
    Abstract: A structure with micro device including a substrate, at least one micro device, and at least one holding structure is provided. The micro device having a top surface is disposed on the substrate, and the top surface is away from the substrate. The holding structure including at least one connecting portion and at least one holding portion is disposed on the substrate. The connecting portion is disposed on at least one edge of the micro device. The holding portion connects the connecting portion and extends to the substrate. From a top view direction, a width of the connecting portion gradually increases from the edge of the micro device to the holding portion.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: October 13, 2020
    Assignee: PlayNitride Inc.
    Inventors: Chih-Ling Wu, Yi-Min Su, Yu-Yun Lo
  • Patent number: 10804189
    Abstract: A package structure of a power device includes a substrate having a first circuit, a first power device, a second power device, an insulation film having a second circuit, at least one electronic component, and a package. The first power device, the second power device, and the insulation film are disposed on the substrate. The first power device and the second power device are directly electrically connected to each other via the first circuit of the substrate. The electronic component is disposed on the insulation film. The package encapsulates the substrate, the first power device, the second power device, and the electronic component.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: October 13, 2020
    Assignee: ACTRON TECHNOLOGY CORPORATION
    Inventor: Hsin-Chang Tsai