Patents Examined by Valerie N Newton
  • Patent number: 11430787
    Abstract: Techniques for forming contacts comprising at least one crystal on source and drain (S/D) regions of semiconductor devices are described. Crystalline S/D contacts can be formed so as to conform to some or all of the top and side surfaces of the S/D regions. Crystalline S/D contacts of the present disclosure are formed by selectively depositing precursor on an exposed portion of one or more S/D regions. The precursor are then reacted in situ on the exposed portion of the S/D region. This reaction forms the conductive, crystalline S/D contact that conforms to the surface of the S/D regions.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: August 30, 2022
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Scott J. Maddox, Cory C. Bomberger, Anand S. Murthy
  • Patent number: 11430871
    Abstract: The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a module substrate, a thinned switch die residing over the module substrate, a first mold compound, and a second mold compound. The thinned switch die includes an electrode region, a number of switch interconnects extending from a bottom surface of the electrode region to the module substrate, an aluminium gallium nitride (AlGaN) barrier layer over a top surface of the electrode region, a GaN buffer layer over the AlGaN barrier layer, and a lateral two-dimensional electron gas (2DEG) layer realized at a heterojunction of the AlGaN barrier layer and the GaN buffer layer. The first mold compound resides over the module substrate, surrounds the thinned switch die, and extends above a top surface of the thinned switch die to form an opening over the top surface of the thinned switch die. The second mold compound fills the opening.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: August 30, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11417571
    Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes a fin structure disposed on a substrate, and first and second gate structures on the fin structure. The first and second gate structures includes first and second interfacial oxide layers, respectively, first and second high-K gate dielectric layers disposed on the first and second IO layers, respectively, and first and second dopant control layers disposed on the first and second HK gate dielectric layers, respectively. The second dopant control layer has a silicon-to-metal atomic concentration ratio greater than an Si-to-metal atomic concentration ratio of the first dopant control layer. The semiconductor further includes first and second work function metal layers disposed on the first and second dopant control layers, respectively, and first and second gate metal fill layers disposed on the first and second work function metal layers, respectively.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: August 16, 2022
    Inventors: Chandrashekhar Prakash Savant, Chia-Ming Tsai, Tien-Wei Yu
  • Patent number: 11411194
    Abstract: A light-emitting device (20) includes a first light-emitting member (10a) and a second light-emitting member (10b). Each of the first light-emitting member (10a) and the second light-emitting member (10b) includes a first surface (12) and a second surface (14), and light is emitted from the first surface (12). The first light-emitting member (10a) includes a first region (16a) and a second region (16b), the first region (16a) of the first light-emitting member (10a) being located on the second surface (14) side of the second light-emitting member (10b) and the second region (16b) of the first light-emitting member (10a) being located on the first surface (12) side of the second light-emitting member (10b).
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: August 9, 2022
    Assignee: PIONEER CORPORATION
    Inventors: Ayako Yoshida, Takashi Chuman, Makoto Matsukawa, Takeru Okada, Chihiro Harada, Akira Hirasawa
  • Patent number: 11411034
    Abstract: A solid-state imaging device according to the present disclosure includes a photoelectric conversion film that is provided outside a semiconductor substrate on a pixel-by-pixel basis, performs photoelectric conversion on light having a predetermined wavelength range, and transmits light having wavelength ranges other than the predetermined wavelength range, and a photoelectric conversion region that is provided inside the semiconductor substrate on a pixel-by-pixel basis and performs photoelectric conversion on the light having the wavelength ranges, the light having the wavelength ranges having passed through the photoelectric conversion film. The photoelectric conversion film includes a film having an avalanche function.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: August 9, 2022
    Assignee: SONY CORPORATION
    Inventors: Nanako Kato, Toshifumi Wakano, Yusuke Otake
  • Patent number: 11404562
    Abstract: Disclosed herein are tunneling field effect transistors (TFETs), and related methods and computing devices. In some embodiments, a TFET may include: a first source/drain material having a p-type conductivity; a second source/drain material having an n-type conductivity; a channel material at least partially between the first source/drain material and the second source/drain material, wherein the channel material has a first side face and a second side face opposite the first side face; and a gate above the channel material, on the first side face, and on the second side face.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: August 2, 2022
    Assignee: Intel Corporation
    Inventors: Cheng-Ying Huang, Willy Rachmady, Matthew V. Metz, Ashish Agrawal, Benjamin Chu-Kung, Uygar E. Avci, Jack T. Kavalieros, Ian A. Young
  • Patent number: 11404680
    Abstract: A pixel bank manufacturing method, a pixel bank structure, a pixel structure, and a display panel are provided. The method includes providing a base substrate, wherein a plurality of anode thin film layers are manufactured on the base substrate; coating a photoresist layer used for covering the plurality of anode thin film layers on the base substrate; performing a photolithography on the photoresist layer by an exposing patterning structure, and baking to cure a remained photoresist layer after the photolithography to form a first bank layer; the exposing patterning structure is a structure that full via holes, first half via holes, a plurality of blind via holes, and second half via holes are arranged repeatedly; forming a second bank layer on the first bank layer; the second bank layer is a black bank layer.
    Type: Grant
    Filed: April 22, 2020
    Date of Patent: August 2, 2022
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventor: Xiaoling Wu
  • Patent number: 11404492
    Abstract: A display device is provided. The display device includes: a display substrate on which a plurality of light-emitting areas are defined; and a color conversion substrate on which a plurality of light-transmitting areas respectively associated with the plurality of light-emitting areas and light-blocking areas between the plurality of light-transmitting areas are defined, the color conversion substrate comprising color patterns in the light-blocking areas, and light-blocking members on the color patterns, wherein at least one of the light-emitting areas has an area smaller than the area of the light-transmitting area that overlaps it in a thickness direction, and the color patterns include a blue colorant.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: August 2, 2022
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jung Bae Song, Shin Moon Kang, Da Hye Kim, Man Gi Kim, Sang Joon Ryu, Seung In Baek, Dae Woo Lee, Yeon Sung Lee, Youn Ho Han
  • Patent number: 11398616
    Abstract: An organic light-emitting display panel and a manufacturing method thereof are provided. A thin-film encapsulation layer in the organic light-emitting panel extends to cover a wall surface of the functional structure layer facing to a light-transmitting hole, and comprehensively protects the functional structure layer and the light-emitting layer.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: July 26, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Qi Ouyang, Mugyeom Kim, Yong Zhao
  • Patent number: 11398529
    Abstract: A display panel and a manufacturing method thereof, the display panel includes a first sub-pixel strip, a second sub-pixel strip, and a third sub-pixel strip arranged in a row direction or a column direction. The sub-pixels on each sub-pixel strip of the present disclosure have the same color and are arranged in series. The first sub-pixels on the first sub-pixel strip and the second sub-pixels on the second sub-pixel strip are staggered to improve flatness of printing the luminous material and luminous uniformity of OLED devices.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: July 26, 2022
    Assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Zhibin Han, Baixiang Han, Jianxin Liu, Liuqi Zhang, Kuo Gao
  • Patent number: 11393780
    Abstract: At least one polymer material may be employed to facilitate bonding between the semiconductor dies. Plasma treatment, formation of a blended polymer, or formation of polymer hairs may be employed to enhance bonding. Alternatively, air gaps can be formed by subsequently removing the polymer material to reduce capacitive coupling between adjacent bonding pads.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: July 19, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ramy Nashed Bassely Said, Senaka Kanakamedala, Raghuveer S. Makala
  • Patent number: 11393844
    Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A stop layer, a first polysilicon layer, a sacrificial layer, a second polysilicon layer, and a dielectric stack are sequentially formed at a first side of a substrate. A channel structure extending vertically through the dielectric stack, the second polysilicon layer, the sacrificial layer, and the first polysilicon layer, stopping at the stop layer, is formed. An opening extending vertically through the dielectric stack and the second polysilicon layer, stopping at the sacrificial layer to expose part of the sacrificial layer, is formed. The sacrificial layer is replaced, through the opening, with a third polysilicon layer between the first and second polysilicon layers. The substrate is removed from a second side opposite to the first side of the substrate, stopping at the stop layer.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: July 19, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Linchun Wu, Kun Zhang, Wenxi Zhou, Zhiliang Xia
  • Patent number: 11387425
    Abstract: A display panel includes: a plurality of light emitting units each having a light emitting side and a back side; a transparent substrate disposed over the light emitting side of the light emitting unit; a transparent film disposed over a side of the transparent substrate opposing the light emitting unit, wherein: the transparent film has an effective refractive index smaller than a refractive index of the transparent substrate; and the transparent film has a position-dependent refractive index progressively smaller along a light emitting direction from the light emitting unit.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: July 12, 2022
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Qun Li
  • Patent number: 11387361
    Abstract: A method for forming a semiconductor structure includes: forming a first gate structure in a predetermined low-potential region of a substrate and a second gate structure in a predetermined high-potential region of the substrate; sequentially forming a first dielectric layer and a second dielectric layer covering the first gate structure and the second gate structure; forming a portion of a third dielectric layer along sidewalls of the second gate structure and on the second dielectric layer; and etching the first dielectric layer and the second dielectric layer with the portion of the third dielectric layer as an etching hard mask to form a first composite spacer covering sidewalls of the first gate structure, and a second composite spacer covering the sidewalls of the second gate structure, wherein a width of the first composite spacer is less than a width of the second composite spacer.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: July 12, 2022
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chin-Hsiu Huang, Tse-Hsiao Liu, Pao-Hao Chiu, Chih-Cherng Liao, Ching-Yi Hsu
  • Patent number: 11380869
    Abstract: The present disclosure provides a display panel including: a substrate; an array layer located on the substrate and including a first inorganic insulating layer, and the first inorganic insulating layer including a first recess in the non-display area; a light-emitting function layer located on the array layer; a thin film encapsulation layer on the light-emitting function layer; and an organic auxiliary layer filled in the first recess. The thin film encapsulation layer includes at least one inorganic encapsulation layer covering the display area and extending to contact and cover the organic auxiliary layer in the first recess; and the at least one inorganic encapsulation layer includes a first opening located on the organic auxiliary layer in the recess. The present disclosure further provides a method of manufacturing the display panel and a display apparatus including the display panel.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: July 5, 2022
    Assignees: WUHAN TIANMA MICRO-ELECTRONICS CO., LTD., WUHAN TIANMA MICROELECTRONICS CO., LTD. SHANGHAI BRANCH
    Inventors: Quanpeng Yu, Zhe Li
  • Patent number: 11380845
    Abstract: A method of making a semi-conducting microfiber. The method includes melting a semi-conducting solid polymer material to form a polymer melt, dipping a tip of a tool into the polymer melt, and lifting the tip of the tool away from the polymer melt, forming a microfiber. A semiconducting microfiber. The semiconducting microfiber contains a non-conjugated semiconducting polymer matrix containing crystalline aggregates with intentionally placed conjugation-break spacers along the polymer backbone. A device containing a plurality of semiconducting microfibers. Each of the semiconducting fibers contains a non-conjugated semiconducting polymer matrix containing crystalline aggregates with intentionally placed conjugation-break spacers along the polymer backbone. An apparatus to make a semiconducting microfiber.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: July 5, 2022
    Assignee: Purdue Research Foundation
    Inventors: Jianguo Mei, Yan Zhao
  • Patent number: 11374102
    Abstract: The present disclosure relates to a FinFET and a manufacturing method of a contact. The manufacturing method comprises steps of: sequentially generating an interlayer dielectric layer, a metal hard mask, an oxide protective cap and a tri-layer mask on a gate to form a device to be etched; photoetching the tri-layer mask to remove photoresist in a non-patterned area; performing main etch on the device to be etched after the photoetching to remove the interlayer dielectric layer in the area that is not covered by the metal hard mask, and the metal hard mask is provided with the oxide protective cap; performing ODL removal on the device to be etched after the main etch to remove remaining part of the tri-layer mask; performing oxide etch on the device to be etched after the ODL removal to remove the oxide protective cap; and generating the contact on the device after the oxide etch. The present disclosure can accurately control the critical dimensions of the contact in an X direction and a Y direction.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: June 28, 2022
    Assignee: SHANGHAI HUALI INTEGRATED CIRCUIT MFG. CO., LTD.
    Inventors: Yongji Mao, Ronghong Ye, Liyao Liu, Yu Zhang, Zhanyuan Hu
  • Patent number: 11374100
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having source or drain structures with a contact etch stop layer are described. In an example, an integrated circuit structure includes a fin including a semiconductor material, the fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first epitaxial source or drain structure is embedded in the fin at the first side of the gate stack. A second epitaxial source or drain structure is embedded in the fin at the second side of the gate stack, the first and second epitaxial source or drain structures including a lower semiconductor layer, an intermediate semiconductor layer and an upper semiconductor layer.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: June 28, 2022
    Assignee: Intel Corporation
    Inventors: Cory Bomberger, Rishabh Mehandru, Anupama Bowonder, Biswajeet Guha, Anand Murthy, Tahir Ghani
  • Patent number: 11362190
    Abstract: A semiconductor device having a substrate, a pair of Group III-Nitride layers on the substrate forming: a heterojunction with a 2 Dimensional Electron Gas (2DEG) channel in a lower one of the pair of Group III-Nitride layers, a cap beryllium doped Group III-Nitride layer on the upper one of the pair of Group III-Nitride layers; and an electrical contact in Schottky contact with a portion of the cap beryllium doped, Group III-Nitride layer.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: June 14, 2022
    Assignee: Raytheon Company
    Inventors: Kiuchul Hwang, Brian D. Schultz, John Logan, Robert E. Leoni, Nicholas J. Kolias
  • Patent number: 11355625
    Abstract: A device includes a first transistor and a second transistor. The first transistor includes a first gate terminal coupled to the first source terminal, a first source terminal, and a first drain terminal. The second transistor includes a second gate terminal coupled to the first drain terminal, a second source terminal, and a second drain terminal.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: June 7, 2022
    Assignees: DELTA ELECTRONICS, INC., NATIONAL CENTRAL UNIVERSITY
    Inventors: Chun-Chieh Yang, Yue-Ming Hsin, Yi-Nan Zhong, Yu-Chen Lai