Abstract: A display device according to an embodiment includes: a substrate including a display area, a dummy area, and a peripheral area; a passivation layer positioned in the display area, the dummy region, and the peripheral area of the substrate; a first adhesive auxiliary layer positioned on the passivation layer and positioned in the dummy region; a dummy pixel defining layer positioned on the first adhesive auxiliary layer and including a hydrophobic material; a second adhesive auxiliary layer positioned on the passivation layer, positioned in the peripheral area, and including a lateral side contacting the dummy pixel defining layer; a common voltage transmitter positioned in the peripheral area; and a common electrode connected to the common voltage transmitter, and positioned on the second adhesive auxiliary layer and the dummy pixel defining layer.

Abstract: An apparatus and method for generating an electrical circuit of semiconductor channel resistor including a first passive element part including a resistor and a capacitor connected in parallel between a first port and a second port, and an ohmic resistor connected in series to the resistor and the capacitor which are connected in parallel are provided. The apparatus includes a substrate selection part configured to receive a selected substrate item; a resistor selection part configured to receive a selected resistor item; a capacitor selection part configured to receive a selected capacitor item; and a circuit generating part configured to generate an electrical circuit from the selected substrate item, the selected resistor item, and the selected capacitor item.

Abstract: The light emitting display apparatus may include a pixel area disposed at a substrate and configured to have an emission area and a non-emission area, a planarization layer disposed at the substrate, and a light emitting device layer disposed at the emission area and the non-emission area above the planarization layer. The light emitting device layer may include a barrier layer disposed at the boundary area between the emission area and the non-emission area. The light emitting display apparatus may be capable of preventing a leakage current between adjacent pixels.

Abstract: A display device includes: a display element layer including an emission area and a non-emission area around the emission area; a first conductive layer on the non-emission area; a first insulating layer on the non-emission area to cover the first conductive layer, the first insulating layer having an opening part overlapping the emission area in a plan view; a second conductive layer on the first insulating layer; and a reflection pattern spaced apart from the second conductive layer and on the first insulating layer.

Abstract: In accordance with an aspect of the present disclosure, in a pattern forming method for a semiconductor device, a first opening is formed in an underlying layer disposed over a substrate. The first opening is expanded in a first axis by directional etching to form a first groove in the underlying layer. A resist pattern is formed over the underlying layer. The resist pattern includes a second opening only partially overlapping the first groove. The underlying layer is patterned by using the resist pattern as an etching mask to form a second groove.

Abstract: A solid-state imaging device including a plurality of pixels including a photoelectric conversion portion, a charge holding portion accumulating a signal charge transferred from the photoelectric conversion portion, and a floating diffusion region to which the signal charge of the charge holding portion is transferred, wherein the photoelectric conversion portion includes a first semiconductor region of a first conductivity type, and a second semiconductor region of a second conductivity type formed under the first semiconductor region, the charge holding portion includes a third semiconductor region of the first conductivity type, and a fourth semiconductor region of the second conductivity type formed under the third semiconductor region, and a p-n junction between the third semiconductor region and the fourth semiconductor region is positioned deeper than a p-n junction between the first semiconductor region and the second semiconductor region.

Abstract: A semiconductor structure with a heat dissipation structure includes a first device wafer includes a front side and a back side. A first transistor is disposed on the front side. The first transistor includes a first gate structure disposed on the front side. Two first source/drain doping regions are embedded within the first device wafer at two side of the first gate structure. A channel region is disposed between the two first source/drain doping regions and embedded within the first device wafer. A first dummy metal structure contacts the back side of the first device wafer, and overlaps the channel region.

Abstract: A method of forming a semiconductor device includes: forming a metal gate structure over a fin that protrudes above a substrate, where the metal gate structure is surrounded by an interlayer dielectric (ILD) layer, where gate spacers extend along opposing sidewalls of the metal gate structure; recessing the metal gate structure and the gate spacers below an upper surface of the ILD layer distal from the substrate; after the recessing, forming a first material over the metal gate structure and over the gate spacers; forming a second material over the first material, where an upper surface of the second material is level with the upper surface of the ILD layer; and removing a first portion of the ILD layer adjacent to the metal gate structure to form an opening that exposes a source/drain region at a first side of the metal gate structure.

Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, a conductive member, a semiconductor member, and an insulating member. The conductive member includes a conductive member end portion and a conductive member other-end portion. The conductive member end portion is between the first electrode and the conductive member other-end portion. The conductive member is electrically connected with one of the second electrode or the third electrode. The semiconductor member includes first to third semiconductor regions. The first semiconductor region includes first and second partial regions. The first partial region is between the first and second electrodes. The second semiconductor region is between the first partial region and the third semiconductor region. The third semiconductor region is electrically connected with the second electrode.

Abstract: An integrated short channel omega gate FinFET and long channel FinFET semiconductor device includes a first fin and second fin on a buried oxide (BOX) layer. The BOX layer includes a fin well outside and substantially adjoining a footprint of a respective fin. A first gate dielectric layer is upon the second fin and a second gate dielectric layer is upon the first dielectric layer. The BOX layer further includes an undercut below the first fin that exposes a portion of a bottom surface of the first fin. An omega-gate is around the first fin. A tri-gate is upon the second gate dielectric layer over the second fin.

Abstract: A display panel, a manufacturing method thereof, and a display device. The display panel includes a base substrate, a first block portion, an encapsulation layer and a touch signal line. The first block portion is located in the peripheral region, the first block portion includes a first block layer and a second block layer; the encapsulation layer covers the first block portion; the touch signal line is located on the encapsulation layer and covers a part of the first block portion. The first block layer includes a first sub-block portion and a second sub-block portion. The second sub-block portion is located between the first sub-block portion and the second block layer, a maximum size of the second sub-block portion is not greater than a minimum size of the first sub-block portion.

Abstract: Some embodiments include an integrated assembly having a stack of alternating insulative levels and conductive levels. A pillar of channel material extends through the stack. The conductive levels have terminal regions adjacent the pillar. Charge-storage-material-segments are adjacent the conductive levels of the stack, and are between the channel material and the terminal regions. Tunneling material is between the charge-storage-material-segments and the channel material. Charge-blocking-material is between the charge-storage-material-segments and the terminal regions. Ribbons of dielectric material extend vertically across the insulative levels and are laterally inset relative to the terminal regions. The ribbons have first regions adjacent the conductive levels and have second regions between the first regions, with the second regions being laterally inset relative to the first regions. Some embodiments include methods of forming integrated assemblies.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain region formed in a semiconductor substrate, a source/drain contact structure formed over the source/drain region, and a gate electrode layer formed adjacent to the source/drain contact structure. The semiconductor device structure also includes a first spacer and a second spacer laterally and successively arranged from the sidewall of the gate electrode layer to the sidewall of the source/drain contact structure. The semiconductor device structure further includes a silicide region formed in the source/drain region. The top width of the silicide region is greater than the bottom width of the source/drain contact structure and less than the top width of the source/drain region.

Abstract: A recessed gate structure includes a recessed structure, wherein the recessed structure comprises a substrate with the recess extending into the substrate from a topmost surface of the substrate; a conductive feature, filled in the recess of the recessed structure; a first functional layer, extending between the conductive feature and the recessed structure, and comprising a first element; a second functional layer, extending between the first functional layer and the conductive feature, and comprising a second element; and an interfacial layer, extending along an interface between the first functional layer and the second functional layer, and comprising the first element and the second element.

Abstract: The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a module substrate, a thinned switch die residing over the module substrate, a first mold compound, and a second mold compound. The thinned switch die includes an electrode region, a number of switch interconnects extending from a bottom surface of the electrode region to the module substrate, an aluminium gallium nitride (AlGaN) barrier layer over a top surface of the electrode region, a GaN buffer layer over the AlGaN barrier layer, and a lateral two-dimensional electron gas (2DEG) layer realized at a heterojunction of the AlGaN barrier layer and the GaN buffer layer. The first mold compound resides over the module substrate, surrounds the thinned switch die, and extends above a top surface of the thinned switch die to form an opening over the top surface of the thinned switch die. The second mold compound fills the opening.

Abstract: The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a module substrate, a thinned switch die residing over the module substrate, a first mold compound, and a second mold compound. The thinned switch die includes an electrode region, a number of switch interconnects extending from a bottom surface of the electrode region to the module substrate, an aluminium gallium nitride (AlGaN) barrier layer over a top surface of the electrode region, a GaN buffer layer over the AlGaN barrier layer, and a lateral two-dimensional electron gas (2DEG) layer realized at a heterojunction of the AlGaN barrier layer and the GaN buffer layer. The first mold compound resides over the module substrate, surrounds the thinned switch die, and extends above a top surface of the thinned switch die to form an opening over the top surface of the thinned switch die. The second mold compound fills the opening.

Abstract: Provided is pixel including a first transistor including a first drain region electrically connected to a light emitting diode, a first gate electrode, a first channel region overlapping the first gate electrode, and a first source region, a first sub-transistor including a first sub-gate electrode, a first sub-channel region overlapping the first sub-gate electrode, a first sub-drain region connected to the first gate electrode, and a first sub-source region, a second sub-transistor including a second sub-gate electrode, a second sub-channel region overlapping the second sub-gate electrode, a second sub-drain region connected to the first sub-source region, and a second sub-source region, and a shielding pattern overlapping the first sub-source region and the second sub-drain region and not overlapping the first sub-channel region, wherein a width of the first sub-channel region is greater than a width of the second sub-channel region.

Abstract: A method includes forming a gate dielectric layer and a dummy gate layer; forming a mask over the dummy gate layer; patterning the gate dielectric layer and the dummy gate layer to form a dummy gate structure, the dummy gate structure including a remaining portion of the gate dielectric layer and a remaining portion of the dummy gate layer; epitaxially growing a first spacer layer on the dummy gate structure and the substrate, in which the first spacer layer has a higher growth rate on the exposed surfaces of the dummy gate structure and the substrate than on exposed surfaces of the mask; doping the first spacer layer to form a doped spacer layer having a different lattice constant than the substrate; depositing a second spacer layer over the doped spacer layer; and etching the second spacer layer and the doped spacer layer to form a gate spacer.

Abstract: The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a module substrate, a thinned switch die residing over the module substrate, a first mold compound, and a second mold compound. The thinned switch die includes an electrode region, a number of switch interconnects extending from a bottom surface of the electrode region to the module substrate, an aluminium gallium nitride (AlGaN) barrier layer over a top surface of the electrode region, a GaN buffer layer over the AlGaN barrier layer, and a lateral two-dimensional electron gas (2DEG) layer realized at a heterojunction of the AlGaN barrier layer and the GaN buffer layer. The first mold compound resides over the module substrate, surrounds the thinned switch die, and extends above a top surface of the thinned switch die to form an opening over the top surface of the thinned switch die. The second mold compound fills the opening.

Abstract: A method for making a semiconductor structure includes forming a first fin and a second fin over a substrate. The method includes forming one or more work function layers over the first and second fins. The method includes forming a nitride-based metal film over the one or more work function layers. The method includes covering the first fin with a patternable layer. The method includes removing a second portion of the nitride-based metal film from the second fin, while leaving a first portion of the nitride-based metal film over the first fin substantially intact.