Patents Examined by Valerie N Newton
  • Patent number: 11538925
    Abstract: Disclosed herein are methods for forming MOSFETs. In some embodiments, a method may include providing a device structure including a plurality of trenches, forming a gate spacer layer over the device structure, and removing the gate spacer layer from a top surface of the device structure and from a first section of each of the plurality of trenches, wherein a portion of the gate spacer layer remains along a second section of each of the plurality of trenches. The method may further include forming a gate oxide layer along the first section of each of the plurality of trenches and along the portion of the gate spacer layer.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: December 27, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Sipeng Gu, Yi Zheng, Qintao Zhang, John Hautala
  • Patent number: 11539020
    Abstract: Provided is a display substrate, a preparation method thereof and a display apparatus. The display substrate includes a base substrate, which has a display area and an encapsulation area, the encapsulation area surrounds the display area, and a hydrophobic structure is arranged on the encapsulation area.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: December 27, 2022
    Assignee: Beijing BOE Technology Development Co., Ltd.
    Inventor: Wenjun Hou
  • Patent number: 11522056
    Abstract: The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a module substrate, a thinned switch die residing over the module substrate, a first mold compound, and a second mold compound. The thinned switch die includes an electrode region, a number of switch interconnects extending from a bottom surface of the electrode region to the module substrate, an aluminium gallium nitride (AlGaN) barrier layer over a top surface of the electrode region, a GaN buffer layer over the AlGaN barrier layer, and a lateral two-dimensional electron gas (2DEG) layer realized at a heterojunction of the AlGaN barrier layer and the GaN buffer layer. The first mold compound resides over the module substrate, surrounds the thinned switch die, and extends above a top surface of the thinned switch die to form an opening over the top surface of the thinned switch die. The second mold compound fills the opening.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: December 6, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11522018
    Abstract: The present disclosure provides a pixel structure, a display panel and a display apparatus. The pixel structure according to an embodiment of the present disclosure includes a pixel structure including: a plurality of pixel units. Each of the plurality of pixel units includes a plurality of sub-pixels, each of the plurality of sub-pixels is divided into at least two target sub-pixels, and a separation region is provided between two adjacent target sub-pixels.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: December 6, 2022
    Assignees: Fuzhou BOE Optoelectronics Technology Co., Ltd., Beijing BOE Technology Development Co., Ltd.
    Inventors: Chengjun Liu, Shaojun Sun, Junxiang Lu, Xia Chen, Yanfei Chi, Junyao Yin, Xiangdong Lin, Guiguang Hu, Haiguang Li
  • Patent number: 11515273
    Abstract: At least one polymer material may be employed to facilitate bonding between the semiconductor dies. Plasma treatment, formation of a blended polymer, or formation of polymer hairs may be employed to enhance bonding. Alternatively, air gaps can be formed by subsequently removing the polymer material to reduce capacitive coupling between adjacent bonding pads.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: November 29, 2022
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Ramy Nashed Bassely Said, Senaka Kanakamedala, Raghuveer S. Makala
  • Patent number: 11509293
    Abstract: An integrated circuit disclosed here includes a first plurality of cell rows, a second plurality of cell rows, first and second clock inverters, and a plurality of flip-flops. The second plurality of cell rows are arranged abutting the first plurality of cell rows. A first number of fins in the first plurality of cell rows is different from a second number of fins in the second plurality of cell rows. The first and second clock inverters are arranged in the second plurality of cell rows. The plurality of flip-flops are arranged in the first plurality of cell rows and the second plurality of cell rows. The plurality of flip-flops include a first plurality of flip-flops configured to operate in response to the first clock and second clock signals.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: November 22, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Chun Wang, Hui-Zhong Zhuang, Chih-Liang Chen, Jerry Chang-Jui Kao, Tzu-Ying Lin
  • Patent number: 11508803
    Abstract: The disclosure discloses an array substrate, a display panel, and a display device. A first power signal line is configured to be formed by electrically connecting a first signal line located in a first source-drain metal layer and a second signal line located in a second source-drain metal layer through a via hole, which is equivalent to that the first power signal line is composed of the first signal line and the second signal line connected in parallel, and the equivalent resistance of the parallel-connected first signal line and second signal line included in the first power signal line is smaller than the resistance of any of the signal lines. Thus, the resistance of the first power signal line may be effectively reduced, so that an IR drop of a display panel with an array substrate may be reduced, and the display uniformity of the display panel is improved.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: November 22, 2022
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Chunping Long, Hui Li
  • Patent number: 11489144
    Abstract: A display device includes a display panel which displays an image, an anti-reflection film disposed on a display surface of the display panel, and a plurality of retardation films disposed on the anti-reflection film. Each of the plurality of retardation films has an in-plane retardation of about 1000 nanometers to about 7000 nanometers.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: November 1, 2022
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sangjae Kim, SeungHwa Ha, Seung-Ho Jung
  • Patent number: 11489050
    Abstract: A normally-off vertical nitride semiconductor transistor device with low threshold voltage variation includes a drift layer containing a nitride semiconductor, a channel region electrically connected to the drift layer, a source electrode, a drain electrode, a gate insulating film, and a gate electrode. The gate insulating film includes at least a first insulating film located at the channel region side, a second insulating film located at the gate electrode side, and a third insulating film between the second insulating film and the gate electrode, wherein the second insulating film has charge traps with energy levels located inside the band gaps of both the first and third insulating films, and the threshold voltage is adjusted by charges accumulated in the charge traps. The threshold voltage is used to block flowing current by substantially eliminating conduction carriers of the channel region by voltage applied to the gate electrode.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: November 1, 2022
    Inventors: Shinichiro Takatani, Riichiro Shirota
  • Patent number: 11488952
    Abstract: A semiconductor device according to some embodiments of the disclosure may include a fin type active pattern extending in a first direction, a plurality of gate structures on the fin type active pattern and extending in a second direction different from the first direction, a plurality of inter-contact insulation patterns on respective ones of the plurality of gate structures, a plurality of interlayer insulation layers on side surfaces of the plurality of gate structures, and a plurality of contact plugs respectively between pairs of the plurality of gate structures. The fin type active pattern may include a plurality of source/drains. Lower ends of the plurality of contact plugs may contact the plurality of source/drains. The plurality of gate structures may each include a first gate metal, a second gate metal, a gate capping layer, a gate insulation layer, a first spacer, and a second spacer.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: November 1, 2022
    Inventors: Sanghyun Lee, Sungwoo Kang, Jongchul Park, Youngmook Oh, Jeongyun Lee
  • Patent number: 11482603
    Abstract: A semiconductor device and a method for forming the semiconductor device are provided. The method includes providing a substrate; forming a fin on the substrate, where the substrate includes a fin dense region and a fin sparse region; forming a gate structure across the fin over the substrate; forming a source-drain doped layer in the fin on both sides of the gate structure; forming a dielectric layer over the substrate, where the dielectric layer covers a top of the gate structure; and forming a first through-hole in the dielectric layer on a side of the gate structure in the fin sparse region, where a bottom of the first through-hole exposes a top sidewall of the gate structure.
    Type: Grant
    Filed: September 18, 2020
    Date of Patent: October 25, 2022
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Nan Wang
  • Patent number: 11482688
    Abstract: A display substrate including a plurality of light emitting elements respectively in a plurality of subpixels configured to emit light for image display is provided. A respective one of the plurality of subpixels includes a base substrate; a first auxiliary cathode; a passivation layer; a first insulating layer; a second auxiliary cathode; a second insulating layer; and a pixel definition layer. The display substrate has a cathode aperture extending through the pixel definition layer and an auxiliary cathode aperture extending through the first insulating layer and the passivation layer. A cathode of a respective one of the plurality of light emitting elements extends into the cathode aperture to electrically connect with the second auxiliary cathode. The second auxiliary cathode extends into the auxiliary cathode aperture to electrically connect with the first auxiliary cathode.
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: October 25, 2022
    Assignees: Hefei BOE Joint Technology Co., Ltd., Beijing BOE Technology Development Co., Ltd.
    Inventors: Can Yuan, Yongqian Li, Zhidong Yuan
  • Patent number: 11476185
    Abstract: Embodiments of the invention include a stacked die system and methods for forming such systems. In an embodiment, the stacked die system may include a first die. The first die may include a device layer and a plurality of routing layers formed over the device layer. The plurality of routing layers may be segmented into a plurality of sub regions. In an embodiment no conductive traces in the plurality of routing layers pass over a boundary between any of the plurality of sub regions. In an embodiment, the stacked die system may also include a plurality of second dies stacked over the first die. According to an embodiment, at least a two of the second dies are communicatively coupled to each other by a die to die interconnect formed entirely within a single sub region in the first die.
    Type: Grant
    Filed: April 1, 2017
    Date of Patent: October 18, 2022
    Assignee: Intel Corporation
    Inventors: MD Altaf Hossain, Dinesh Somasekhar, Dheeraj Subbareddy
  • Patent number: 11469214
    Abstract: Aspects of the disclosure relate to forming stacked NAND with multiple memory sections. Forming the stacked NAND with multiple memory sections may include forming a first memory section on a sacrificial substrate. A logic section may be formed on a substrate. The logic section may be bonded to the first memory section. The sacrificial substrate may be removed from the first memory section and a second memory section having a second sacrificial substrate may be formed and bonded to the first memory section.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: October 11, 2022
    Assignee: Xcelsis Corporation
    Inventors: Stephen Morein, Javier A. Delacruz, Xu Chang, Belgacem Haba, Rajesh Katkar
  • Patent number: 11456373
    Abstract: In an embodiment, a device includes: a fin on a substrate, fin having a Si portion proximate the substrate and a SiGe portion distal the substrate; a gate stack over a channel region of the fin; a source/drain region adjacent the gate stack; a first doped region in the SiGe portion of the fin, the first doped region disposed between the channel region and the source/drain region, the first doped region having a uniform concentration of a dopant; and a second doped region in the SiGe portion of the fin, the second doped region disposed under the source/drain region, the second doped region having a graded concentration of the dopant decreasing in a direction extending from a top of the fin to a bottom of the fin.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: September 27, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Ling Chan, Liang-Yin Chen, Wei-Ting Chien
  • Patent number: 11430871
    Abstract: The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a module substrate, a thinned switch die residing over the module substrate, a first mold compound, and a second mold compound. The thinned switch die includes an electrode region, a number of switch interconnects extending from a bottom surface of the electrode region to the module substrate, an aluminium gallium nitride (AlGaN) barrier layer over a top surface of the electrode region, a GaN buffer layer over the AlGaN barrier layer, and a lateral two-dimensional electron gas (2DEG) layer realized at a heterojunction of the AlGaN barrier layer and the GaN buffer layer. The first mold compound resides over the module substrate, surrounds the thinned switch die, and extends above a top surface of the thinned switch die to form an opening over the top surface of the thinned switch die. The second mold compound fills the opening.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: August 30, 2022
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11430787
    Abstract: Techniques for forming contacts comprising at least one crystal on source and drain (S/D) regions of semiconductor devices are described. Crystalline S/D contacts can be formed so as to conform to some or all of the top and side surfaces of the S/D regions. Crystalline S/D contacts of the present disclosure are formed by selectively depositing precursor on an exposed portion of one or more S/D regions. The precursor are then reacted in situ on the exposed portion of the S/D region. This reaction forms the conductive, crystalline S/D contact that conforms to the surface of the S/D regions.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: August 30, 2022
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Scott J. Maddox, Cory C. Bomberger, Anand S. Murthy
  • Patent number: 11417571
    Abstract: A semiconductor device with different gate structure configurations and a method of fabricating the same are disclosed. The semiconductor device includes a fin structure disposed on a substrate, and first and second gate structures on the fin structure. The first and second gate structures includes first and second interfacial oxide layers, respectively, first and second high-K gate dielectric layers disposed on the first and second IO layers, respectively, and first and second dopant control layers disposed on the first and second HK gate dielectric layers, respectively. The second dopant control layer has a silicon-to-metal atomic concentration ratio greater than an Si-to-metal atomic concentration ratio of the first dopant control layer. The semiconductor further includes first and second work function metal layers disposed on the first and second dopant control layers, respectively, and first and second gate metal fill layers disposed on the first and second work function metal layers, respectively.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: August 16, 2022
    Inventors: Chandrashekhar Prakash Savant, Chia-Ming Tsai, Tien-Wei Yu
  • Patent number: 11411034
    Abstract: A solid-state imaging device according to the present disclosure includes a photoelectric conversion film that is provided outside a semiconductor substrate on a pixel-by-pixel basis, performs photoelectric conversion on light having a predetermined wavelength range, and transmits light having wavelength ranges other than the predetermined wavelength range, and a photoelectric conversion region that is provided inside the semiconductor substrate on a pixel-by-pixel basis and performs photoelectric conversion on the light having the wavelength ranges, the light having the wavelength ranges having passed through the photoelectric conversion film. The photoelectric conversion film includes a film having an avalanche function.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: August 9, 2022
    Assignee: SONY CORPORATION
    Inventors: Nanako Kato, Toshifumi Wakano, Yusuke Otake
  • Patent number: 11411194
    Abstract: A light-emitting device (20) includes a first light-emitting member (10a) and a second light-emitting member (10b). Each of the first light-emitting member (10a) and the second light-emitting member (10b) includes a first surface (12) and a second surface (14), and light is emitted from the first surface (12). The first light-emitting member (10a) includes a first region (16a) and a second region (16b), the first region (16a) of the first light-emitting member (10a) being located on the second surface (14) side of the second light-emitting member (10b) and the second region (16b) of the first light-emitting member (10a) being located on the first surface (12) side of the second light-emitting member (10b).
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: August 9, 2022
    Assignee: PIONEER CORPORATION
    Inventors: Ayako Yoshida, Takashi Chuman, Makoto Matsukawa, Takeru Okada, Chihiro Harada, Akira Hirasawa