Abstract: A display panel includes: a plurality of light emitting units each having a light emitting side and a back side; a transparent substrate disposed over the light emitting side of the light emitting unit; a transparent film disposed over a side of the transparent substrate opposing the light emitting unit, wherein: the transparent film has an effective refractive index smaller than a refractive index of the transparent substrate; and the transparent film has a position-dependent refractive index progressively smaller along a light emitting direction from the light emitting unit.

Abstract: A method for forming a semiconductor structure includes: forming a first gate structure in a predetermined low-potential region of a substrate and a second gate structure in a predetermined high-potential region of the substrate; sequentially forming a first dielectric layer and a second dielectric layer covering the first gate structure and the second gate structure; forming a portion of a third dielectric layer along sidewalls of the second gate structure and on the second dielectric layer; and etching the first dielectric layer and the second dielectric layer with the portion of the third dielectric layer as an etching hard mask to form a first composite spacer covering sidewalls of the first gate structure, and a second composite spacer covering the sidewalls of the second gate structure, wherein a width of the first composite spacer is less than a width of the second composite spacer.

Abstract: The present disclosure provides a display panel including: a substrate; an array layer located on the substrate and including a first inorganic insulating layer, and the first inorganic insulating layer including a first recess in the non-display area; a light-emitting function layer located on the array layer; a thin film encapsulation layer on the light-emitting function layer; and an organic auxiliary layer filled in the first recess. The thin film encapsulation layer includes at least one inorganic encapsulation layer covering the display area and extending to contact and cover the organic auxiliary layer in the first recess; and the at least one inorganic encapsulation layer includes a first opening located on the organic auxiliary layer in the recess. The present disclosure further provides a method of manufacturing the display panel and a display apparatus including the display panel.

Abstract: A method of making a semi-conducting microfiber. The method includes melting a semi-conducting solid polymer material to form a polymer melt, dipping a tip of a tool into the polymer melt, and lifting the tip of the tool away from the polymer melt, forming a microfiber. A semiconducting microfiber. The semiconducting microfiber contains a non-conjugated semiconducting polymer matrix containing crystalline aggregates with intentionally placed conjugation-break spacers along the polymer backbone. A device containing a plurality of semiconducting microfibers. Each of the semiconducting fibers contains a non-conjugated semiconducting polymer matrix containing crystalline aggregates with intentionally placed conjugation-break spacers along the polymer backbone. An apparatus to make a semiconducting microfiber.

Abstract: The present disclosure relates to a FinFET and a manufacturing method of a contact. The manufacturing method comprises steps of: sequentially generating an interlayer dielectric layer, a metal hard mask, an oxide protective cap and a tri-layer mask on a gate to form a device to be etched; photoetching the tri-layer mask to remove photoresist in a non-patterned area; performing main etch on the device to be etched after the photoetching to remove the interlayer dielectric layer in the area that is not covered by the metal hard mask, and the metal hard mask is provided with the oxide protective cap; performing ODL removal on the device to be etched after the main etch to remove remaining part of the tri-layer mask; performing oxide etch on the device to be etched after the ODL removal to remove the oxide protective cap; and generating the contact on the device after the oxide etch. The present disclosure can accurately control the critical dimensions of the contact in an X direction and a Y direction.

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, integrated circuit structures having source or drain structures with a contact etch stop layer are described. In an example, an integrated circuit structure includes a fin including a semiconductor material, the fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first epitaxial source or drain structure is embedded in the fin at the first side of the gate stack. A second epitaxial source or drain structure is embedded in the fin at the second side of the gate stack, the first and second epitaxial source or drain structures including a lower semiconductor layer, an intermediate semiconductor layer and an upper semiconductor layer.

Abstract: A semiconductor device having a substrate, a pair of Group III-Nitride layers on the substrate forming: a heterojunction with a 2 Dimensional Electron Gas (2DEG) channel in a lower one of the pair of Group III-Nitride layers, a cap beryllium doped Group III-Nitride layer on the upper one of the pair of Group III-Nitride layers; and an electrical contact in Schottky contact with a portion of the cap beryllium doped, Group III-Nitride layer.

Abstract: A device includes a first transistor and a second transistor. The first transistor includes a first gate terminal coupled to the first source terminal, a first source terminal, and a first drain terminal. The second transistor includes a second gate terminal coupled to the first drain terminal, a second source terminal, and a second drain terminal.

Abstract: A device includes a complementary metal-oxide-semiconductor (CMOS) wafer and a conductive shielding layer. The CMOS wafer includes a semiconductor substrate, at least one front-end-of-the-line (FEOL) element, at least one back-end-of-the-line (BEOL) element and at least one dielectric layer. The FEOL element is disposed on the semiconductor substrate, the dielectric layer is disposed on the semiconductor substrate, and the BEOL element is disposed on the dielectric layer. The conductive shielding layer is disposed on the dielectric layer, in which the conductive shielding layer is electrically connected to the semiconductor substrate. an orthogonal projection of the conductive shielding layer on the semiconductor substrate does not overlap with an orthogonal projection of the FEOL element on the semiconductor substrate.

Abstract: According to the disclosed embodiments, an on-die capacitor utilized in energy-harvest based circuits is provided. In the disclosed design, the harvester is coupled to the on-die capacitor, thus there is no need to provide power interfaces and semi-conductor devices external to the IC. The disclosed design of the on-die capacitor would reduce the overall size and cost of the IC.

Abstract: The structure of a field-effect transistor with a source-down configuration and process of making the transistor are described in this paper. The transistor is built in a semiconductor chip with a trench extending from top chip surface towards the bottom surface. The trench contains a conductive gate material embedded in a dielectric material in the trench. A conductive field plate is also embedded in the trench and extends from the top surface of the chip towards the bottom surface of the chip and splits the conductive gate electrode into two halves. The conductive field plate penetrates the trench and makes electrical contact with the heavily doped substrate near the bottom surface of the chip.

Abstract: An epitaxial structure includes a substrate, a buffer layer, a back diffusion barrier layer, a channel layer formed on the back diffusion barrier layer, and a barrier layer formed on the channel layer. The buffer layer is formed on the substrate. The back diffusion barrier layer is formed on the buffer layer. The chemical composition of the back diffusion barrier layer is AlxInyGa1-x-yN, wherein 0?x?1 and 0?y?1. The lattice constant of the back diffusion barrier layer is between 2.9 ? and 3.5 ?. The back diffusion barrier layer is composed of a plurality of regions in the thickness direction, and the aluminum (Al) content and the indium (In) content of the back diffusion barrier layer are changed stepwise or gradually changed stepwise along the thickness direction. The back diffusion barrier layer further includes carbon, and the carbon concentration is changed stepwise or gradually changed stepwise along the thickness direction.

Abstract: Image sensors are provided. An image sensor includes a color filter layer. The image sensor includes a metal structure adjacent a sidewall of the color filter layer. The image sensor includes an insulating layer on the color filter layer. Moreover, the image sensor includes an electrode layer on the insulating layer. Methods of forming image sensors are also provided.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a substrate; an isolation layer in a first trench, defining an active region of the substrate; a gate structure in a second trench intersecting the active region; and first and second impurity regions spaced apart from each other by the gate structure. The gate structure includes a gate dielectric layer in the second trench; a first metal layer on the gate dielectric layer; and a gate capping layer on the first metal layer. The gate dielectric layer includes D+ and ND2+ in an interface region, adjacent the first metal layer, and D is deuterium, N is nitrogen, and D+ is positively-charged deuterium.

Abstract: The disclosed technology relates generally to the field of semiconductor devices, and more particularly to co-integration of GaN-based devices with Si-based devices. In one aspect, a method of forming a semiconductor device includes forming a first wafer including, on a front side thereof, a III-V semiconductor layer stack formed on a first substrate and a first bonding layer. The III-V semiconductor layer stack includes a GaN-based device layer structure formed on the first substrate. The method additionally includes, subsequent to forming the first wafer, bonding the first bonding layer to a second bonding layer of a second wafer. The second wafer includes a second silicon substrate supporting an active device layer, a back-end-of-line interconnect structure and the second bonding layer. The method further comprises, subsequent to bonding, thinning the first wafer from a backside, wherein thinning includes removing at least the first substrate.

Abstract: A semiconductor device includes a substrate, at least two gate spacers, and a gate stack. The substrate has at least one semiconductor fin. The gate spacers are disposed on the substrate. At least one of the gate spacers has a sidewall facing to another of the gate spacers. The gate stack is disposed between the gate spacers. The gate stack includes a high-? dielectric layer and a gate electrode. The high-? dielectric layer is disposed on the substrate and covers at least a portion of the semiconductor fin while leaving the sidewall of said at least one gate spacer uncovered. The gate electrode is disposed on the high-? dielectric layer.

Abstract: Disclosed are a semiconductor structure, which includes a charge-trapping sidewall spacer-type non-volatile memory (CTSS-NVM) device, and a method of forming the structure. The CTSS-NVM device includes asymmetric first and second sidewall spacers on opposing sidewalls of a gate structure above a channel region in a semiconductor substrate. The second sidewall spacer is wider than the first and includes multiple dielectric spacer layers, one of which is made of a charge-trapping material, is separated from the substrate (e.g., by a thin oxide layer), and has a bottom end closest to the substrate with a maximum width that is sufficient to achieve charge-trapping for proper CTSS-NVM device operation. The CTSS-NVM device further includes an epitaxial semiconductor layer for a source/drain region on the semiconductor substrate adjacent to the first sidewall spacer and a metal silicide layer for a Schottky barrier on the semiconductor substrate adjacent to the second sidewall spacer.

Abstract: A high electron mobility transistor includes a channel layer, a barrier layer, a first compound semiconductor layer, and a second compound semiconductor layer. The channel layer is disposed on the substrate, and the barrier layer is disposed on the channel layer. The first compound semiconductor layer is disposed on the barrier layer. The second compound semiconductor layer is disposed between the barrier layer and the first compound semiconductor layer, where the first compound semiconductor layer and the second compound semiconductor layer include a concentration distribution of metal dopant, and the concentration distribution of metal dopant includes a first peak in the first compound semiconductor layer and a second peak in the second compound semiconductor layer.

Abstract: A method of manufacturing a light emitting device includes: providing a substrate including a pair of connection terminals, the connection terminals each having a protruding portion at least on a first main surface of the connection terminal; providing a light emitting element on the protruding portion, the light emitting element having a semiconductor laminate and a pair of electrodes on a same surface of the semiconductor laminate; bonding the pair of the electrodes of the light emitting element and the pair of the connection terminals, respectively, by a molten material; and embedding a surface of the protruding portion of the connection terminals, a surface of the molten material, and a space between the substrate and the light emitting element into a light reflecting member.

Abstract: The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a module substrate, a thinned switch die residing over the module substrate, a first mold compound, and a second mold compound. The thinned switch die includes an electrode region, a number of switch interconnects extending from a bottom surface of the electrode region to the module substrate, an aluminium gallium nitride (AlGaN) barrier layer over a top surface of the electrode region, a GaN buffer layer over the AlGaN barrier layer, and a lateral two-dimensional electron gas (2DEG) layer realized at a heterojunction of the AlGaN barrier layer and the GaN buffer layer. The first mold compound resides over the module substrate, surrounds the thinned switch die, and extends above a top surface of the thinned switch die to form an opening over the top surface of the thinned switch die. The second mold compound fills the opening.