Patents Examined by Valerie N Newton
  • Patent number: 11696464
    Abstract: A display panel, a manufacturing method thereof and a display device are provided. The display panel includes a display area and a hole forming area, where the display area surrounds the hole forming area, and an organic material layer is provided in the hole forming area so that a height difference between the hole forming area and the display area is less than a threshold value of 4 um.
    Type: Grant
    Filed: July 10, 2020
    Date of Patent: July 4, 2023
    Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xuwu Hu, Yangsheng Liu, Mengxia Kong, Yuheng Qiu, Wei Lin
  • Patent number: 11688783
    Abstract: The present disclosure provides a semiconductor device having a buried wordline. The semiconductor device includes a substrate having a surface and a first dielectric layer extending from the surface of the substrate into the substrate. The semiconductor device also includes a second dielectric layer disposed on the first dielectric layer and extending from the surface of the substrate into the substrate and a first conductive layer disposed in the substrate and separated from the substrate by the first dielectric layer and the second dielectric layer.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: June 27, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chuan-Lin Hsiao
  • Patent number: 11682689
    Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: June 20, 2023
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Francois Roy, Sonarith Chhun
  • Patent number: 11682593
    Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: June 20, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzuan-Horng Liu, Chen-Hua Yu, Hsien-Pin Hu, Tzu-Yu Wang, Wei-Cheng Wu, Shang-Yun Hou, Shin-Puu Jeng
  • Patent number: 11677002
    Abstract: A semiconductor structure includes a substrate, a channel layer, a barrier layer, a source structure, a drain structure, a doped compound semiconductor layer, a dielectric layer, and a gate structure. The channel layer is disposed on the substrate. The barrier layer is disposed on the channel layer. The source structure and the drain structure are disposed on opposite sides of the barrier layer. The doped compound semiconductor layer is disposed on the barrier layer. The doped compound semiconductor layer has a first side adjacent to the source structure and a second side adjacent to the drain structure. The doped compound semiconductor layer has at least one opening exposing at least a portion of the barrier layer. The dielectric layer is disposed on the doped compound semiconductor layer and the barrier layer. The gate structure is disposed on the doped compound semiconductor layer.
    Type: Grant
    Filed: September 16, 2020
    Date of Patent: June 13, 2023
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shin-Cheng Lin, Chih-Hung Lin, Po-Heng Lin
  • Patent number: 11676999
    Abstract: An electronic device includes a dielectric layer including crystal grains having aligned crystal orientations the dielectric layer may be between a substrate and a gate electrode. The dielectric layer may be between isolated first and second electrodes. A method of manufacturing an electronic device may include preparing a substrate having a channel layer, forming the dielectric layer on the channel layer, and forming a gate electrode on the dielectric layer.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: June 13, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sanghyun Jo, Eunha Lee, Jinseong Heo, Junghwa Kim, Hyangsook Lee, Seunggeol Nam
  • Patent number: 11677007
    Abstract: A layout of a semiconductor device stored on a non-transitory computer-readable medium includes a first transistor in an active device region, the first transistor comprising a first channel region a first source region and a first drain region. The layout further includes a second transistor in a guard ring region, the second transistor comprising a second channel region a second source region and a second drain region. The second channel region includes a semiconductor material having a higher thermal conductivity than a semiconductor material of the first channel region.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Amit Kundu, Jaw-Juinn Horng
  • Patent number: 11667817
    Abstract: A conductive film includes an elongated release film and a plurality of conductive adhesive film pieces provided on the release film. Then, the plurality of adhesive film pieces are arranged in a longitudinal direction X of the release film. For this reason, the adhesive film piece can be set to an arbitrary shape. Accordingly, it is possible to attach the adhesive film piece to adhesive surfaces having various shapes and to efficiently use the adhesive film piece.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: June 6, 2023
    Assignee: Showa Denko Materials Co., Ltd.
    Inventors: Takashi Tatsuzawa, Kazuya Matsuda, Yutaka Tsuchida, Takashi Seki, Mitsuyoshi Shimamura, Kengo Shinohara, Tetsuyuki Shirakawa, Yasunori Kawabata, Satoru Matsumoto
  • Patent number: 11665927
    Abstract: An organic light emitting diode display device includes a substrate including at least one subpixel having a non-emitting area and an emitting area; a thin film transistor in the non-emitting area on the substrate; an overcoating layer on the thin film transistor and having a plurality of microlenses at a top surface of the overcoating layer; and a light emitting diode in the emitting area on the overcoating layer and connected to the thin film transistor, wherein a surface of the plurality of microlenses in a sampling area of the emitting area is divided into a plurality of convex portions and a plurality of concave portions with respect to a central surface, and a total volume of the plurality of convex portions with respect to the central surface is equal to a total volume of the plurality of concave portions with respect to the central surface.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: May 30, 2023
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Keum-Kyu Min, Min-Geun Choi, Yong-Hoon Choi
  • Patent number: 11658087
    Abstract: A high resistivity wafer with a heat dissipation structure includes a high resistivity wafer and a metal structure. The high resistivity wafer includes a heat dissipation region and a device support region. The high resistivity wafer consists of an insulating material. The metal structure is only embedded within the heat dissipation region of the high resistivity wafer. The metal structure surrounds the device support region.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: May 23, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Kuo-Yuh Yang, Chia-Huei Lin
  • Patent number: 11659716
    Abstract: A method of forming memory circuitry comprises using a digitline mask to form both: (a) conductive digitlines in a memory array area, and (b) lower portions of conductive vias in a peripheral circuitry area laterally of the memory array area. The lower portions of the vias electrically couple with circuitry below the vias and the digitlines. Pairs of conductive wordlines are formed above the digitlines in the memory array area. The pairs of wordlines extend from the memory array area into the peripheral circuitry area. Individual of the pairs are directly above individual of the lower portions of individual of the vias. Individual upper portions of the individual vias are formed. The individual upper portions both: (c) directly electrically couple to one of the individual lower portions of the individual vias, and (d) directly electrically couple together the wordlines of the individual pair of wordlines that are directly above the respective one individual lower portion of the respective individual via.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: May 23, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Werner Juengling
  • Patent number: 11659736
    Abstract: Disclosed is a light emitting display device which may block lateral leakage current. The light emitting display device includes electrode patterns arranged under a bank between adjacent subpixels so as to form a vertical channel, the bank covered by the electrode patterns functions as a gate insulating film and thus dielectric polarization occurs therein, and charges move from a common layer having high hole mobility to a common layer having low hole mobility, thereby being capable of preventing lateral leakage current.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: May 23, 2023
    Assignee: LG Display Co., Ltd.
    Inventor: Sung-Ji Yoon
  • Patent number: 11652166
    Abstract: A method of forming a power semiconductor device includes providing an epi layer over a substrate; forming a well at an upper portion of the epi layer; forming a pillar below the well and spaced apart from the well to define a Schottky contact region; etching a trench into the epi layer, the trench having a sidewall and a base, a portion of the sidewall of the trench corresponding to the Schottky contact region; forming a metal contact layer over the sidewall and the base of the trench, the metal contact layer forming a Schottky interface with the epi layer at the Schottky contact region; and forming a gate electrode and first and second electrodes.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: May 16, 2023
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Wonhwa Lee, Gary H. Loechelt
  • Patent number: 11653553
    Abstract: A functional layer forming ink used in forming a functional layer of the self-luminous element by a printing method, the ink including functional material dissolved or dispersed in a mixed solvent including solvents having different boiling points. When one or more solvents are selected from the solvents of the mixed solvent in descending order of boiling point until a mass ratio of the selection to the mixed solvent is a defined ratio or more, the one or more solvents in the selection are included in a solvent group of solvents that have a contact angle of 5° or less with respect to a defined resin material.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: May 16, 2023
    Assignee: JOLED INC.
    Inventor: Masakazu Takata
  • Patent number: 11652017
    Abstract: A high resistivity wafer with a heat dissipation structure includes a high resistivity wafer and a metal structure. The high resistivity wafer includes a heat dissipation region and a device support region. The high resistivity wafer consists of an insulating material. The metal structure is only embedded within the heat dissipation region of the high resistivity wafer. The metal structure surrounds the device support region.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: May 16, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Purakh Raj Verma, Kuo-Yuh Yang, Chia-Huei Lin
  • Patent number: 11652144
    Abstract: The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a module substrate, a thinned switch die residing over the module substrate, a first mold compound, and a second mold compound. The thinned switch die includes an electrode region, a number of switch interconnects extending from a bottom surface of the electrode region to the module substrate, an aluminium gallium nitride (AlGaN) barrier layer over a top surface of the electrode region, a GaN buffer layer over the AlGaN barrier layer, and a lateral two-dimensional electron gas (2DEG) layer realized at a heterojunction of the AlGaN barrier layer and the GaN buffer layer. The first mold compound resides over the module substrate, surrounds the thinned switch die, and extends above a top surface of the thinned switch die to form an opening over the top surface of the thinned switch die. The second mold compound fills the opening.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: May 16, 2023
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11639551
    Abstract: A display apparatus includes a substrate on which a central area and a peripheral area adjacent to the central area are arranged. The central area includes a display area. The display apparatus further includes: at least one insulation pattern that is formed in the peripheral area; a groove from which a material for forming the insulation pattern is removed and that is formed adjacent to the insulation pattern; and at least one insulating layer that is interposed between the insulation pattern and the substrate. The groove is located in the at least one insulating layer.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: May 2, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventor: Sun-Youl Lee
  • Patent number: 11638383
    Abstract: A method of manufacturing a display device includes preparing a substrate, wherein the substrate includes a pixel area and a transmission area, forming insulating layers in the pixel area and in the transmission area, forming a pixel electrode on the insulating layers in the pixel area and forming a pixel-defining layer on the pixel electrode, wherein the pixel-defining layer exposes at least part of the pixel electrode, forming a metal layer on the pixel-defining layer in the pixel area, the at least part of the pixel electrode exposed by the pixel-defining layer in the pixel area, and the insulating layers in the transmission area, removing the metal layer on the insulating layers in the transmission area, and removing the insulating layers in the transmission area.
    Type: Grant
    Filed: June 4, 2020
    Date of Patent: April 25, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jongchan Lee, Kibum Kim, Myeonghun Song, Jeonghyun Lee, Sanghee Jang, Woonghee Jeong
  • Patent number: 11637076
    Abstract: A system and method for adding a source contact, a drain contact, and an apparent gate contact to a FinFET having a fin including a source region, a drain region, and a gate disposed over the fin forming one or more transistor junctions with the fin. The method comprises producing a source contact opening extending downward to a first region electrically coupled to the source region, a drain contact opening extending downward to a second region electrically coupled to the drain region, and a gate contact opening extending downward to a third region electrically isolated from the gate, and filling the source contact opening, the drain contact opening, and the gate contact opening with a conductive metal.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: April 25, 2023
    Assignee: RAMBUS INC.
    Inventors: Lap Wai Chow, Bryan J. Wang, James P. Baukus, Ronald P. Cocchi
  • Patent number: 11621327
    Abstract: The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a module substrate, a thinned switch die residing over the module substrate, a first mold compound, and a second mold compound. The thinned switch die includes an electrode region, a number of switch interconnects extending from a bottom surface of the electrode region to the module substrate, an aluminium gallium nitride (AlGaN) barrier layer over a top surface of the electrode region, a GaN buffer layer over the AlGaN barrier layer, and a lateral two-dimensional electron gas (2DEG) layer realized at a heterojunction of the AlGaN barrier layer and the GaN buffer layer. The first mold compound resides over the module substrate, surrounds the thinned switch die, and extends above a top surface of the thinned switch die to form an opening over the top surface of the thinned switch die. The second mold compound fills the opening.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: April 4, 2023
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll