Abstract: The present disclosure provides a display substrate, a method for manufacturing the same, and a display device. The display substrate includes: a base substrate; a plurality of light emitting units on the base substrate, where the plurality of light emitting units include a plurality of pixel display areas; and a reflection layer on the base substrate. The reflection layer includes a plurality of patterns and a plurality of openings defined between adjacent patterns of the plurality of patterns, and positions of the plurality of openings are corresponding to positions of the plurality of pixel display areas.

Abstract: A method of manufacturing a display apparatus includes forming a thin-film transistor on a substrate and forming a planarization layer to cover the thin-film transistor, forming, on the planarization layer, a pixel electrode electrically connected to the thin-film transistor and a pixel defining layer exposing at least a center portion of the pixel electrode, and defining at least one groove having a closed curve shape at a location corresponding to a second non-display area. When the thin-film transistor is formed, a voltage line is also formed at a location corresponding to a first non-display area. When the at least one groove is formed, a portion of the planarization layer disposed between the pad area and the display area is simultaneously removed such that a portion of the voltage line between the pad area and the display area is exposed.

Abstract: A semiconductor device includes: a first electrode; a first semiconductor layer of first conductivity type provided on the first electrode; a second semiconductor layer of first conductivity type provided on the first semiconductor layer; a first semiconductor region of second conductivity type provided on the second semiconductor layer; a second semiconductor region of second conductivity type provided on the second semiconductor layer; a first insulating film provided in a trench between the first semiconductor region and the second semiconductor region, the trench reaching the second semiconductor layer from above the first semiconductor region and the second semiconductor region, the first insulating film containing silicon oxide; a second electrode provided in the trench, the second electrode facing the second semiconductor layer via the first insulating film, the second electrode containing polysilicon; a third electrode provided above the second electrode, the third electrode facing the first semicondu

Abstract: The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a module substrate, a thinned switch die residing over the module substrate, a first mold compound, and a second mold compound. The thinned switch die includes an electrode region, a number of switch interconnects extending from a bottom surface of the electrode region to the module substrate, an aluminium gallium nitride (AlGaN) barrier layer over a top surface of the electrode region, a GaN buffer layer over the AlGaN barrier layer, and a lateral two-dimensional electron gas (2DEG) layer realized at a heterojunction of the AlGaN barrier layer and the GaN buffer layer. The first mold compound resides over the module substrate, surrounds the thinned switch die, and extends above a top surface of the thinned switch die to form an opening over the top surface of the thinned switch die. The second mold compound fills the opening.

Abstract: There is provided a display element, including: a display region including pixels arranged in a two-dimensional form, each of the pixels including a plurality of sub pixels. In each pixel, a height of a light reflecting portion with respect to a light emitting portion is adjusted for each sub pixel.

Abstract: A display substrate includes a base substrate and an encapsulation film disposed at a first side of the base substrate. At least one corner of an edge of the encapsulation film is a rounded corner or a substantially rounded corner.

Abstract: According to one embodiment, a semiconductor device includes first, second, third electrodes, a semiconductor member, and a first compound member. The third electrode is between the first and second electrodes in a first direction from the first to second electrodes. The semiconductor member includes first and second semiconductor regions. The first semiconductor region includes first, second, third, fourth, and fifth partial regions. A second direction from the first partial region to the first electrode crosses the first direction. The fourth partial region is between the first and third partial regions in the first direction. The fifth partial region is between the third and second partial regions in the first direction. The second semiconductor region includes first and second semiconductor portions. The first compound member includes first, second and third compound regions.

Abstract: In a method for forming a semiconductor device, a layer of logic devices is formed on a substrate. The layer of logic devices includes a stack of gate-all-around field-effect transistors (GAA-FETs) positioned over the substrate, where the stack of GAA-FETs includes a first layer of GAA-FETs stacked over a second layer of GAA-FETs. A first wiring layer is formed over the layer of logic devices, where the first wiring layer includes one or more metal routing levels. A memory stack is formed over the first wiring layer. The memory stack includes wordline layers and insulating layers that alternatingly arranged over the first wiring layer. A three-dimensional (3D) NAND memory device is formed in the memory stack. The 3D NAND memory device includes a channel structure that extends into the memory stack and further is coupled to the wordline layers of the memory stack.

Abstract: An organic light emitting device and a method of manufacturing the same are provided. The organic light emitting device, from bottom to top, includes a substrate, an indium tin oxide layer, a semiconductor layer, and a pixel defining layer. The semiconductor layer covers foreign particles on the indium tin oxide layer to make the indium tin oxide layer have an even thickness. The method of manufacturing the organic light emitting device including steps of providing an indium tin oxide layer, providing a semiconductor layer, patterning, and providing a pixel defining layer. The disclosure prevents from uneven brightness (mura) causing from a bright spot or a dark spot appearing at the foreign particles and ensures an overall even brightness of the organic light emitting device by providing the semiconductor layer disposed on the indium tin oxide layer to cover foreign particles on the indium tin oxide layer.

Abstract: Disclosed is a light emitting panel and a display device. The light emitting panel includes a substrate, wherein the substrate comprises a display area, a non-display area and a bending area connecting the display area and the non-display area; a transistor layer, wherein the transistor layer is disposed on the substrate and disposed relative to the display area and the non-display area; an organic layer, wherein the organic layer is disposed on the substrate and disposed relative to the bending area; and a wiring layer, wherein the wiring layer is disposed on the organic layer; wherein a vertical height of the organic layer is greater than a vertical height of the transistor layer.

Abstract: A display apparatus includes: a base substrate; a thin film transistor disposed on the base substrate and including an active pattern; an insulating layer disposed on the active pattern of the thin film transistor; a connection electrode disposed on the insulating layer, and electrically connected to the thin film transistor, wherein the connection electrode includes a curved wiring portion; a first via insulating layer covering the connection electrode; a first electrode disposed on the first via insulating layer; a light emitting layer disposed on the first electrode and at least partially overlapping the connection electrode; and a second electrode disposed on the light emitting layer.

Abstract: A display device includes: in a display area, a first transistor including a first gate electrode; a second transistor electrically connected to the first transistor, including a second gate electrode; a light-emitting element; and in a peripheral area surrounding the display area, a power wiring including: first and second power wiring patterns spaced apart from each other; and a bridge pattern connecting the first and second power wiring patterns; a signal wiring; and an insulating layer covering the power wiring and the signal wiring, and a part of the insulating layer is removed to form an organic layer-removed area, the bridge pattern overlapping the organic layer-removed area, the power wiring and the signal wiring overlap each other in the organic layer-removed area, the signal wiring and the bridge pattern are disposed in a same layers as the first gate electrode and the second gate electrode, respectively.

Abstract: According to an aspect of the present disclosure, a light emitting display device includes a substrate defined by a plurality of sub-pixels and a first overcoating layer disposed on the substrate, a connection electrode and a sacrificial layer disposed on the first overcoating layer, a first electrode disposed on the connection electrode, a second overcoating layer disposed on the sacrificial layer and including an opening that exposes a portion of the first electrode, a dummy first electrode disposed on a top surface of the second overcoating layer and a side surface of the opening and separated from the first electrode, a bank layer covering the dummy first electrode and a portion of the first electrode, and an emission layer and a second electrode disposed on the first electrode and the bank layer.

Abstract: Provided is a display substrate, a preparation method thereof and a display apparatus. The display substrate includes a base substrate, which has a display area and an encapsulation area, the encapsulation area surrounds the display area, and a hydrophobic structure is arranged on the encapsulation area.

Abstract: Disclosed herein are methods for forming MOSFETs. In some embodiments, a method may include providing a device structure including a plurality of trenches, forming a gate spacer layer over the device structure, and removing the gate spacer layer from a top surface of the device structure and from a first section of each of the plurality of trenches, wherein a portion of the gate spacer layer remains along a second section of each of the plurality of trenches. The method may further include forming a gate oxide layer along the first section of each of the plurality of trenches and along the portion of the gate spacer layer.

Abstract: The present disclosure provides a pixel structure, a display panel and a display apparatus. The pixel structure according to an embodiment of the present disclosure includes a pixel structure including: a plurality of pixel units. Each of the plurality of pixel units includes a plurality of sub-pixels, each of the plurality of sub-pixels is divided into at least two target sub-pixels, and a separation region is provided between two adjacent target sub-pixels.

Abstract: The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a module substrate, a thinned switch die residing over the module substrate, a first mold compound, and a second mold compound. The thinned switch die includes an electrode region, a number of switch interconnects extending from a bottom surface of the electrode region to the module substrate, an aluminium gallium nitride (AlGaN) barrier layer over a top surface of the electrode region, a GaN buffer layer over the AlGaN barrier layer, and a lateral two-dimensional electron gas (2DEG) layer realized at a heterojunction of the AlGaN barrier layer and the GaN buffer layer. The first mold compound resides over the module substrate, surrounds the thinned switch die, and extends above a top surface of the thinned switch die to form an opening over the top surface of the thinned switch die. The second mold compound fills the opening.

Abstract: At least one polymer material may be employed to facilitate bonding between the semiconductor dies. Plasma treatment, formation of a blended polymer, or formation of polymer hairs may be employed to enhance bonding. Alternatively, air gaps can be formed by subsequently removing the polymer material to reduce capacitive coupling between adjacent bonding pads.

Abstract: An integrated circuit disclosed here includes a first plurality of cell rows, a second plurality of cell rows, first and second clock inverters, and a plurality of flip-flops. The second plurality of cell rows are arranged abutting the first plurality of cell rows. A first number of fins in the first plurality of cell rows is different from a second number of fins in the second plurality of cell rows. The first and second clock inverters are arranged in the second plurality of cell rows. The plurality of flip-flops are arranged in the first plurality of cell rows and the second plurality of cell rows. The plurality of flip-flops include a first plurality of flip-flops configured to operate in response to the first clock and second clock signals.

Abstract: The disclosure discloses an array substrate, a display panel, and a display device. A first power signal line is configured to be formed by electrically connecting a first signal line located in a first source-drain metal layer and a second signal line located in a second source-drain metal layer through a via hole, which is equivalent to that the first power signal line is composed of the first signal line and the second signal line connected in parallel, and the equivalent resistance of the parallel-connected first signal line and second signal line included in the first power signal line is smaller than the resistance of any of the signal lines. Thus, the resistance of the first power signal line may be effectively reduced, so that an IR drop of a display panel with an array substrate may be reduced, and the display uniformity of the display panel is improved.