Abstract: A multilayer reflection electrode film includes a Ag film that is formed of Ag or an Ag alloy; and a transparent conductive oxide film that is disposed on the Ag film, in which the transparent conductive oxide film is formed of an oxide that includes Zn and Ga and further includes one element or two or more elements selected from the group consisting of Sn, Y, and Ti.

Abstract: A cooler (1) has a cooling plate (1a), a cooling fin (1b) provided on a center portion of a lower surface of the cooling plate (1a), and a lower projection (1c) provided on a peripheral portion of the lower surface of the cooling plate (1a). A semiconductor device (3) is provided on an upper surface of the cooling plate (1a). A bus bar (5) is connected to the semiconductor device (3). A cooling mechanism (8) encloses a lower surface and a lateral surface of the cooler (1). An O-ring (9) is provided between a lower surface of the lower projection (1c) and a bottom surface of the cooling mechanism (8). A bolt (10) penetrates a sidewall of the cooling mechanism (8) and screws the cooler (1) to the cooling mechanism (8).

Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein a nitride diffusion barrier (NDB) has a L2/L1/NL or NL/L1/L2 configuration wherein NL is a metal nitride or metal oxynitride layer, L2 blocks oxygen diffusion from an adjoining Hk enhancing layer, and L1 prevents nitrogen diffusion from NL to the free layer (FL) thereby enhancing magnetoresistive ratio and FL thermal stability, and minimizing resistance x area product for the MTJ. NL is the uppermost layer in a bottom spin valve configuration, or is formed on a seed layer in a top spin valve configuration such that L2 and L1 are always between NL and the FL or pinned layer, respectively. In other embodiments, one or both of L1 and L2 are partially oxidized. Moreover, either L2 or L1 may be omitted when the other of L1 and L2 is partially oxidized. A spacer between the FL and L2 is optional.

Abstract: In one example embodiment, a SOT-MRAM includes a storage unit having a Co?X?Pt? based free layer. The storage unit includes a bottom electrode and the Co?X?Pt? based free layer is disposed over the bottom electrode. Further, the storage unit includes a tunnel barrier layer over the Co?X?Pt? based free layer, and a fixed layer over the tunnel barrier layer. The Co?X?Pt? based free layer, tunnel barrier layer and fixed layer form a magnetic tunnel junction. The storage unit may also include a top electrode over the MTJ.

Abstract: Provided is pixel including a first transistor including a first drain region electrically connected to a light emitting diode, a first gate electrode, a first channel region overlapping the first gate electrode, and a first source region, a first sub-transistor including a first sub-gate electrode, a first sub-channel region overlapping the first sub-gate electrode, a first sub-drain region connected to the first gate electrode, and a first sub-source region, a second sub-transistor including a second sub-gate electrode, a second sub-channel region overlapping the second sub-gate electrode, a second sub-drain region connected to the first sub-source region, and a second sub-source region, and a shielding pattern overlapping the first sub-source region and the second sub-drain region and not overlapping the first sub-channel region, wherein a width of the first sub-channel region is greater than a width of the second sub-channel region.

Abstract: In a general aspect, an electronic device assembly can include a dielectric substrate having a first surface and a second surface opposite the first surface and a leadframe including: a first leadframe portion including a first plurality of signal leads; and a second leadframe portion including a second plurality of signal leads. The substrate can be coupled with a subset of the first plurality of signal leads and a subset of the second plurality of signal leads. Signal leads of the first plurality of signal leads, other than the subset of the first plurality of signal leads, can be spaced from the dielectric substrate. Signal leads of the second plurality of signal leads, other than the subset of the second plurality of signal leads, can be spaced from the dielectric substrate. The assembly can further include first and second semiconductor die that are electrically coupled with the substrate and the leadframe portions.

Abstract: The back reflection in photodiodes is caused by an abrupt index contrast between the input waveguide and the composite waveguide/light absorbing material. In order to improve the back reflection, it is proposed to introduce an angle between the waveguide and the leading edge of the light absorbing material. The angle will result in gradually changing the effective index between the index of the waveguide and the index of the composite section, and consequently lower the amount of light reflecting back.

Abstract: An electronic device may have a flexible organic light-emitting diode display layer. The edge of the flexible display layer may be bent. The display may have pixels formed from organic light-emitting diodes having anodes characterized by anode surface normals. For pixels in some regions of the display such as the bent edge of the display, the display may be characterized by a display surface normal for a pixel that differs from an anode surface normal for the anode of the organic light-emitting diode of that pixel. By tilting the anodes in this way, color shifts due to off-axis viewing of the pixels in the bend edge of the display can be minimized. If desired, tilted anodes may have multiple areas with different tilts. Sets of pixels with different anode tilts or other characteristics that differ may be supplied with common pixel data values.

Abstract: A pixel, is provided the pixel comprising: a photodiode structure built on top of an integrated circuit generating a charge; the integrated circuit comprising at least one semiconductor material and at least one interconnect layer; the at least one interconnect layer comprises an interconnect to facilitate charge flowing into a collection node disposed in the semiconductor material; the interconnect being in contact with a doped contact diffusion disposed proximate to the collection node; a transfer transistor disposed between the collection node and a conversion node, the conversion node coupled to an active transistor; the pixel having a reset configured to reset the conversion node.

Abstract: An image sensor includes a first organic photoelectric conversion layer on a base layer, a floating diffusion region in the base layer, a first storage node including a first electrode layer, which is configured to receive a bias signal, a first portion of a first semiconductor layer which includes a semiconductor material, and a first portion of a first dielectric layer. The first dielectric layer extends between the first electrode layer and the first semiconductor layer. The first storage node is electrically connected to the first organic photoelectric conversion layer. The image sensor includes a first transfer transistor including the first dielectric layer, the first semiconductor layer, and a first transfer gate electrode which is configured to receive first transfer control signal. The first transfer transistor has a first end electrically connected to the first storage node and a second end electrically connected to the floating diffusion region.

Abstract: A display device includes a substrate, regions on the substrate each including a transparent first and a second regions, one or more light-emitting elements disposed in the second region, and a circular polarizing pattern disposed in front of the pixel regions. Each of the one or more light-emitting elements includes a reflective electrode and a transparent electrode layered one above the other, and a light-emitting film provided between the transparent electrode and the reflective electrode. The light-emitting film is configured to emit light in response to electric current supplied between the reflective electrode and the transparent electrode. The circular polarizing pattern covers the entire reflective electrode when seen from the front of the display device. At least a part of the first region is located within a gap in the circular polarizing pattern when seen from the front of the display device.

Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.

Abstract: An integrated circuit device includes a substrate including a fin active region extending in a first direction, a gate line intersecting the fin active region and extending in a second direction perpendicular to the first direction, a power line electrically connected to source/drain regions at sides of the gate line on the fin active region, a pair of dummy gate lines intersecting the fin active region and extending in the second direction, and a device separation structure electrically connected to the pair of dummy gate lines and including a lower dummy contact plug between the pair of dummy gate lines on the fin active region and electrically connected to the power line, and an upper dummy contact plug on the lower dummy contact plug and on the pair of dummy gate lines to electrically connect the lower dummy contact plug to the pair of dummy gate lines.

Abstract: A semiconductor device according to an embodiment includes first conductors, a second conductor, a first semiconductor, a multi-layered body, and a third conductor. The second conductor is provided above the first conductors. The multi-layered body is provided between the first semiconductor and the first conductors, and between the first semiconductor and the second conductor. The third conductor is provided between the multi-layered body and the second conductor. The first semiconductor includes a first portion facing an uppermost first conductor and a second portion facing the second conductor. The first semiconductor is continuous at least from the first portion to the second portion.

Abstract: An organic light emitting diode display device includes a substrate, light emitting structures, fan-out wirings, and a wiring structure. The substrate has a display region including a light emitting region and a peripheral region surrounding the light emitting region and a pad region located in one side of the display region. The light emitting structures are disposed in the light emitting region on the substrate. The fan-out wirings are disposed in the peripheral region on the substrate, and the fan-out wirings include a straight-line portion and an oblique line portion. The wiring structure is disposed on the fan-out wirings, and includes a conductive layer and conductive patterns spaced apart from each other and disposed on the conductive layer.

Abstract: Resistive memory cells, precursors thereof, and methods of making resistive memory cells are described. In some embodiments, the resistive memory cells are formed from a resistive memory precursor that includes a switching layer precursor containing a plurality of oxygen vacancies that are present in a controlled distribution therein, optionally without the use of an oxygen exchange layer. In these or other embodiments, the resistive memory precursors described may include a second electrode formed on a switching layer precursor, wherein the second electrode is includes a second electrode material that is conductive but which does not substantially react with oxygen. Devices including resistive memory cells are also described.

Abstract: A method of forming memory circuitry comprises using a digitline mask to form both: (a) conductive digitlines in a memory array area, and (b) lower portions of conductive vias in a peripheral circuitry area laterally of the memory array area. The lower portions of the vias electrically couple with circuitry below the vias and the digitlines. Pairs of conductive wordlines are formed above the digitlines in the memory array area. The pairs of wordlines extend from the memory array area into the peripheral circuitry area. Individual of the pairs are directly above individual of the lower portions of individual of the vias. Individual upper portions of the individual vias are formed. The individual upper portions both: (c) directly electrically couple to one of the individual lower portions of the individual vias, and (d) directly electrically couple together the wordlines of the individual pair of wordlines that are directly above the respective one individual lower portion of the respective individual via.

Abstract: A wiring board includes: a Cu pad; an insulating layer covering the Cu pad and having an opening portion; a first metallic layer formed on the Cu pad in the opening portion; and a connecting terminal formed on the first metallic layer to extend from the opening portion to above an upper surface of the insulating layer. The connecting terminal includes: a seed layer formed on the first metallic layer; and a second metallic layer formed on the seed layer. A stacked body is formed of the first metallic layer and the connecting terminal and includes a constricted portion. The constricted portion is located in a certain position of the first metallic layer in a thickness direction of the first metallic layer, and a sectional area of the stacked body is the smallest at the constricted portion.

Abstract: A wafer-level process for manufacturing solid state lighting (“SSL”) devices using large-diameter preformed metal substrates is disclosed. A light emitting structure is formed on a growth substrate, and a preformed metal substrate is bonded to the light emitting structure opposite the growth substrate. The preformed metal substrate can be bonded to the light emitting structure via a metal-metal bond, such as a copper-copper bond, or with an inter-metallic compound bond.

Abstract: Embodiments of the present disclosure relate to quantum circuit assemblies implementing superconducting qubits, e.g., transmons, in which SQUID loops and portions of FBLs configured to magnetically couple to the SQUID loops extend substantially vertically. In contrast to conventional implementations, for a vertical SQUID according to various embodiments of the present disclosure, a line that is perpendicular to the SQUID loop is parallel to the qubit substrate. A corresponding FBL is also provided in a vertical arrangement, in order to achieve efficient magnetic coupling to the vertical SQUID loop, by ensuring that at least a portion of the FBL designed to conduct current responsible for generating magnetic field for tuning qubit frequency is substantially perpendicular to the substrate.