Abstract: A method for forming a wide band gap semiconductor device is provided. The method includes forming a gate insulation layer on a wide band gap semiconductor substrate and annealing the gate insulation layer using at least a first reactive gas species and a second reactive gas species, wherein the first reactive gas species differs from the second reactive gas species. The method can include forming a gate electrode on the gate insulation layer after annealing the gate insulation layer.

Abstract: A structure to increase the breakdown voltage of the high electron mobility transistor is provided to solve the problem of function loss under a high voltage state. The structure includes a substrate, a conducting layer located on the substrate, a gate insulating layer and an electric-field-dispersion layer. The upper portion of the conducting layer is an electron supply layer, and the lower portion of the conducting layer is an electron tunnel layer. The gate insulating layer is laminated on the electron supply layer. The electric-field-dispersion layer is laminated on the gate insulating layer. The dielectric constant of the electric-field-dispersion layer is smaller than that of the gate insulating layer. A gate electrode is located between the electric-field-dispersion layer and the gate insulating layer. A source and a drain electrodes are respectively electrically connected to the electric-field-dispersion layer, the gate insulating layer, the electron supply layer, and the electron tunnel layer.

Abstract: This disclosure provides devices and methods for 3-D device packaging with backside interconnections. One or more device elements can be hermetically sealed from an ambient environment, such as by vacuum lamination and bonding. One or more via connections provide electrical interconnection from a device element to a back side of a device substrate, and provide electrical interconnection from the device substrate to external circuitry on the back side of the device. The external circuitry can include a printed circuit board or flex circuit. In some implementations, an electrically conductive pad is provided on the back side, which is electrically connected to at least one of the via connections. In some implementations, the one or more via connections are electrically connected to one or more electrical components or interconnections, such as a TFT or a routing line.

Abstract: Embodiments of the invention include methods of forming a textile patterned hardmask. In an embodiment, a first hardmask and a second hardmask are formed over a top surface of an interconnect layer in an alternating pattern. A sacrificial cross-grating may then be formed over the first and second hardmasks. In an embodiment, portions of the first hardmask that are not covered by the sacrificial cross-grating are removed to form first openings and a third hardmask is disposed into the first openings. Embodiments may then include etching through portions of the second hardmask that are not covered by the sacrificial cross-grating to form second openings. The second openings may be filled with a fourth hardmask. According to an embodiment, the first, second, third, and fourth hardmasks are etch selective to each other. In an embodiment the sacrificial cross-grating may then be removed.

Abstract: Vertical memory devices and method of manufacturing the same are disclosed. The vertical memory device includes a substrate having a cell block area, a block separation area and a boundary area, a plurality of stack structures arranged in the cell block area and the boundary area such that insulation interlayer patterns are stacked on the substrate alternately with the electrode patterns. The stack structures are spaced apart by the block separation area in the third direction. A plurality of channel structures extend through the stack structures to the substrate in the cell block area in the first direction and are connected to the substrate. A plurality of dummy channel structures extend through upper portions of each of the stack structures in the boundary area and are connected to a dummy bottom electrode pattern spaced apart from the substrate. The bridge defect is thus substantially prevented near the substrate.

Abstract: The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a module substrate, a thinned switch die residing over the module substrate, a first mold compound, and a second mold compound. The thinned switch die includes an electrode region, a number of switch interconnects extending from a bottom surface of the electrode region to the module substrate, an aluminium gallium nitride (AlGaN) barrier layer over a top surface of the electrode region, a GaN buffer layer over the AlGaN barrier layer, and a lateral two-dimensional electron gas (2DEG) layer realized at a heterojunction of the AlGaN barrier layer and the GaN buffer layer. The first mold compound resides over the module substrate, surrounds the thinned switch die, and extends above a top surface of the thinned switch die to form an opening over the top surface of the thinned switch die. The second mold compound fills the opening.

Abstract: A semiconductor element includes an enhancement-type transistor structure with a layer construction including a base substrate, a first semiconductor layer, and a second semiconductor layer, which are arranged one on top of the other along a first direction. The transistor structure further has a source electrode, a gate electrode, and a drain electrode, which are spaced apart from one another along a second direction that is transverse to the first direction. The first and second semiconductor layers are formed by different group III nitride materials, such that a 2D electron gas forms in a boundary region of the first and second semiconductor layers. The first and second semiconductor layers have holes in the region of the gate electrode, between which holes multiple fins including the group III nitride materials remain. The gate electrode has a plurality of gate fingers extending into the holes.

Abstract: A display apparatus includes: a base substrate having a front surface, a rear surface opposite to the front surface, a module hole extending through the front surface and the rear surface, an active area, a peripheral area adjacent to the active area, and a margin area adjacent to the module hole; a circuit layer on the base substrate, the circuit layer including a driving element including a thin film transistor; a display element layer including: a deposition preventing pattern; and a light emitting element including: a first electrode connected to the thin film transistor; an emission pattern on the first electrode; and a second electrode disposed on the emission pattern. An encapsulation layer is on the display element layer, and encapsulating the light emitting element. The second electrode and the deposition preventing pattern are at a same layer and do not overlap with each other.

Abstract: A method for forming a self-aligned contact includes providing a substrate with a plurality of gate structures formed on the substrate. The method also includes forming a spacer liner on the gate structures and the substrate. The method also includes forming a sacrificial layer between the gate structures and on the gate structures. The method also includes forming a plurality of dielectric plugs through the sacrificial layer above the gate structures. The method also includes removing the sacrificial layer to form a plurality of contact openings between the gate structures. The method also includes forming an etch resistant layer conformally covering the sidewall and the bottom of the contact openings. The method also includes forming a plurality of contact plugs in the contact openings.

Abstract: An array substrate is disclosed. The array substrate may include a base substrate (21), a pixel defining layer (22) on the base substrate (21), and a charge generating layer (24) above the pixel defining layer (22). The pixel defining layer (22) may define a plurality of pixel regions. The pixel defining layer (22) may include a plurality of acoustic structures (220), and each of the plurality of acoustic structures (220) may be configured to resonate under an action of an acoustic wave of a threshold frequency to form a slit to disconnect the charge generating layer (24) of two adjacent pixel regions of the plurality of pixel regions.

Abstract: An IC device includes a simultaneously formed capacitor and resistor structure. The capacitor and resistor may be located between a Back End of the Line (BEOL) interconnect stack and an external device interconnect pad of the IC device. The resistor may be used to step down a voltage applied across the resistor. The resistor may include one or more resistor plates that are formed simultaneously with a respective one or more plates of the capacitor. For example, a capacitor plate and a resistor plate may be patterned and formed from the same conductive sheet. Each of the resistor plates may be connected to one or more vertical interconnect accesses (VIA).

Abstract: Semiconductor packages having a first layer interconnect portion that includes a coaxial interconnect between a die and a package substrate are described. In an example, the package substrate includes a substrate-side coaxial interconnect electrically connected to a signal line. The die is mounted on the package substrate and includes a die-side coaxial interconnect coupled to the substrate-side coaxial interconnect. The coaxial interconnects can be joined by a solder bond between respective central conductors and shield conductors.

Abstract: A semiconductor device includes a III-nitride buffer layer and a III-nitride barrier layer. A boron nitride alloy interlayer interposed between the III-nitride buffer layer and the III-nitride barrier layer. A portion of the III-nitride buffer layer includes a two-dimensional electron gas (2DEG) channel that is on a side of the III-nitride buffer layer adjacent to the boron nitride alloy interlayer.

Abstract: A display device is provided. The display device includes a display region which includes a first display region and a second display region, where the first display region includes a plurality of first pixels, and the second display region includes a plurality of second pixels and at least one light transmission region, where the light transmission region has light transmittance that is higher than light transmittance of the first pixel and light transmittance of the second pixel, and the second display region has light transmittance that is higher than light transmittance of the first display region.

Abstract: A semiconductor structure with a back gate includes a device wafer includes a front side and a back side. A transistor is disposed on the front side, wherein the transistor includes a gate structure, a source and a drain. An interlayer dielectric covers the transistor. A first metal layer and a second metal layer are within the interlayer dielectric. A first conductive plug is within the interlayer dielectric and contacts the source and the first metal layer. A second conductive plug is disposed within the interlayer dielectric and contacts the drain and the second metal layer. A back gate, a source conductive pad and a drain conductive pad are disposed on the back side. A first via plug penetrates the device wafer to electrically connect the source conductive pad and the source. A second via plug penetrates the device wafer to electrically connect the drain conductive pad and the drain.

Abstract: A semiconductor device includes: a conductive layer M(h) including first and second power grid (PG) segments and first routing segments which are conductive, where h is an integer and h?1; long axes of the first and second PG segments and the first routing segments extending in a first direction; the first and second PG segments being separated in a second direction by a PG gap having a midpoint, the second direction being substantially perpendicular to the first direction. The first routing segments are distributed: between the first and second PG segments; and substantially uniformly in the second direction with respect to the midpoint of the PG gap.

Abstract: Fabricating a multilevel composite semiconductor structure includes providing a first substrate comprising a first material; dicing a second substrate to provide a plurality of dies; mounting the plurality of dies on a third substrate; joining the first substrate and the third substrate to form a composite structure; and joining a fourth substrate and the composite structure.

Abstract: A display device includes a substrate, an auxiliary electrode, a buffer layer, a plurality of active elements, and a plurality of light-emitting elements. The auxiliary electrode is disposed on the substrate and overlapped with an active region. The buffer layer is disposed on the auxiliary electrode. The plurality of active elements are disposed on the buffer layer and disposed in the active region. The plurality of light-emitting elements are electrically connected with the active elements, respectively. Each of the light-emitting elements includes a first electrode, a second electrode, and a light-emitting layer disposed between the first electrode and the second electrode. Each of the second electrodes is electrically connected with the auxiliary electrode.

Abstract: A drift structure having a drift zone of a first conductivity type is formed in a SiC semiconductor body of a semiconductor component. Transistor cells each include a doping region and a source region in the SiC semiconductor body. The doping region forms a first pn junction with the drift structure and a second pn junction with the source region. The doping region is electrically connected to a first load electrode. A diode region is formed between the transistor cells and a side surface of the SiC semiconductor body. The diode region is electrically connected to the first load electrode and forms a third pn junction with the drift structure. An emitter efficiency of the diode region is higher than an emitter efficiency of the doping region.

Abstract: The present disclosure relates to a Gallium-Nitride (GaN) based module, which includes a module substrate, a thinned switch die residing over the module substrate, a first mold compound, and a second mold compound. The thinned switch die includes an electrode region, a number of switch interconnects extending from a bottom surface of the electrode region to the module substrate, an aluminium gallium nitride (AlGaN) barrier layer over a top surface of the electrode region, a GaN buffer layer over the AlGaN barrier layer, and a lateral two-dimensional electron gas (2DEG) layer realized at a heterojunction of the AlGaN barrier layer and the GaN buffer layer. The first mold compound resides over the module substrate, surrounds the thinned switch die, and extends above a top surface of the thinned switch die to form an opening over the top surface of the thinned switch die. The second mold compound fills the opening.