Abstract: An advanced multi-bit magnetic random access memory device and a method for writing to the advanced multi-bit magnetic random access memory device. The magnetic memory includes one or more pair-cells. A pair-cell is two memory cells. Each memory cell has a magnetic multilayer structure. The structure includes a magnetically changeable ferromagnetic layer, a ferromagnetic reference layer having a non-changeable magnetization state, and a corresponding spacer layer separating the ferromagnetic layers. The memory cells are arranged such that an effective remnant magnetization of each of the cells is non-parallel from the cells' long-axis. This allows for more than one-bit to be stored as well as for efficient writing and reduced power consumption.

Abstract: A non-volatile memory device and drive method thereof uses a voltage bias condition to enable an electronic device to normally operate without employing a specific transistor, e.g., a recall transistor. The non-volatile memory device performs its function normally without the recall transistor, and by which a degree of cell integration can be considerably raised. A SRAM latch is controlled by the logic circuit, a SONOS (silicon-oxide-nitride-oxide-silicon) transistor is electrically connected to a Vcc node of the electronic device to store a high/low state of the SRAM latch according to a turn-on or turn-off state of power, and a pass transistor controls read, program, and erase operations of the SONOS transistor.

Abstract: An improved method and device for column decoding for flash memory devices utilizes a burst page with a length greater than the length of a logical page. When a misalignment of an initial address occurs, valid reads across logical page boundaries are possible. The memory device enters the wait state only when a read crosses a burst page boundary. This minimizes the amount of time in which the memory device enters the wait state. In the preferred embodiment, this is achieved with a different management of the control signals that feed the third level of a three-level decoding stage column decoder. Changes to the architecture or in the number of column decoder selectors are not required. The memory access time during synchronous reads is thus improved.

Abstract: An integrated semiconductor memory device includes a control circuit with a mode register to store operating parameters, as well as further registers to store further operating parameters. An operating parameter is selectively written to or read from one of the registers for storage of an operating parameter as a function of a first or second state of a configuration signal that is applied to an address connection. Any subsequent write and read access to one of the registers for storage of an operating parameter takes place analogously to a write and read access to a memory cell in a memory cell array. The integrated semiconductor memory device is thus operated to allow writing and reading of operating parameters using a standard interface and a standard protocol for inputting and outputting data to and from the memory cell array.

Abstract: A sensing amplifier comprising a program cell current sensing circuit, an erase cell current sensing circuit and a latch circuit is provided. Each of the program and erase cell current sensing circuits further comprises a plurality of program/erase memory cells, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor and a fourth PMOS transistor. Wherein, one of the drain/source of the first NMOS transistor is electrically coupled to both the program/erase memory cells and a gate of the third NMOS transistor to form a node. In addition, one of the drain/source of the third NMOS transistor is coupled to the latch circuit. Moreover, the program/erase memory cell provides a program/erase current to the first NMOS transistor. The latch circuit will be driven once the amount of the electric charges accumulated at the node caused by the program/erase current overcomes a threshold voltage of the third NMOS transistor.

Abstract: An apparatus and technique for testing of multi-level cells (MLC) in a memory storage device using a high bandwidth data path architecture. The technique includes hardware for obtaining a first data and a second data from a multilevel cell memory. The first data is different from the second data. The first data and second data are compared and, based at least in part on this comparison, the multilevel cell memory is programmed. Programming the multilevel cell memory includes accessing memory cells in the multilevel cell memory and determining the number of bits per memory cell of the first data that need programming.

Abstract: A semiconductor device includes a plurality of memory cells, and an error-correction circuit. Its write operation is performed by a late-write method, and ECC processing is executed in parallel with writing to shorten a cycle time. Moreover, when a memory cell is power-supplied through a well tap, the same address is not assigned while the memory cell is power-supplied through the well tap.

Abstract: A semiconductor device includes a first nonvolatile memory element group which includes a plurality of first nonvolatile memory elements programmed with data by electrically and irreversibly varying device characteristics, a verify circuit which detects a defective first nonvolatile memory element in the first nonvolatile memory element group, and a second nonvolatile memory element group which includes a plurality of second nonvolatile memory elements programmed with data by electrically and irreversibly varying device characteristics and which stores address data to rescue the defective first nonvolatile memory element.

Abstract: A storage circuit using a dual-access memory includes means for alternately activating one access, then the other, with a maximum frequency equal to twice the maximum possible frequency of activation of a given access. At least two successive activations of the means control operations of the same type, either reading or writing operations.

Abstract: A system and method for avoiding offset in and reducing the footprint of a non-volatile memory that has a plurality of memory bank circuits. Each memory bank circuit has memory cells coupled to sense amplifiers, row and column decoders coupled to the memory cells, and bias circuits coupled to the sense amplifiers. The system includes a reference cell matrix coupled to each of the plurality of memory bank circuits. The reference cell matrix is configured to provide reference cell current for each of the plurality of memory bank circuits.

Abstract: A test circuit employs hardware to test a memory cell in a memory block. The address of an error cell detected is stored in a first or second error address register. Access made by a processor to the address of the error cell would be detected by a first or second address comparator. Data is then written to a first or second correction register, which serves as an alternative cell, or data is read from one of the registers.

Abstract: A one-time programmable (OTP) cell includes an access transistor coupled to an antifuse transistor. Access transistor has a gate oxide thickness that is greater than the gate oxide thickness of the antifuse transistor so that if the antifuse transistor is programmed, the voltage felt across the gate/drain junction of the access transistor is insufficient to cause the gate oxide of the access transistor to break down. The dual gate oxide OTP cell may be used in an array in which only one OTP cell is programmed at a time. The dual gate oxide OTP cell also may be used in an array in which several OTP cells are programmed simultaneously.

Abstract: Methods and apparatuses for adjusting trim settings for internally generated voltages of an integrated circuit device are provided. In one embodiment the apparatus receives a target digital value for an internally generated voltage, and compares the target digital value to a current digital value for the internally generated voltage. If the comparison indicates that a difference between the target digital value and the current digital value is greater than an allowable threshold, a trim setting used to trim the internally generated voltage is adjusted based on the difference. The trim setting may be adjusted until the difference between the target digital value and the current digital value is less than or equal to the allowable threshold.

Abstract: A buffer circuit includes a plurality of registers, a write register selector, a read register selector, and an address proximity detector. The write register selector operates in synchronism with a write clock signal and outputs write enable signals in a predetermined sequence for write-enabling the plurality of registers, one at a time. The read register selector operates in synchronism with a read clock signal and outputs read enable signals in the predetermined sequence for read-enabling the plurality of registers to be read, one at a time. The address proximity detector detects an event in which a difference between a register write-enabled by one of the write enable signals and a different register read-enabled by one of the read enable signals at a time in the predetermined sequence is equal to a predetermined value and outputs a reset signal upon detecting such event.

Abstract: A nonvolatile integrated circuit memory device includes a memory cell array having a plurality of memory cells. A high voltage generating unit generates first, second, and third program voltages used in programming the memory cell array. A program control unit controls times of applying the second and third program voltages to the memory cell array responsive to the first program voltage. Programming methods for the nonvolatile integrated circuit memory devices are also provided.

Abstract: During an erasing sequence, after a preprogram operation (S1), an erasing operation (S3), and an APDE operation (S5) are executed and confirmation by an APDE verify operation (S6: P) and confirmation by an erase-verify operation (S7: P) are completed, step A is executed prior to a soft-program operation (S10) of a plurality of memory cells. A dummy memory cell program operation (S8) is continuously executed until a completion of a program operation is confirmed by a dummy memory cell program verify operation (S9). By execution of the program operation on the dummy memory cells, a voltage stress similar to that of a program operation is applied to memory cells in an over-erased state via bit lines. Thereby, the over-erased state is reduced thereby lowering a column leak current. Erroneous recognition during a soft-program verify operation (S11) can be prevented, and excessive soft-programming can be avoided.

Abstract: A nonvolatile semiconductor memory device is provided having a plurality of electrically rewritable nonvolatile memory cells connected in series together. A select gate transistor is connected in series to the serial combination of memory cells. A certain one of the memory cells which is located adjacent to the select gate transistor is for use as a dummy cell. This dummy cell is not used for data storage. During data erasing, the dummy cell is applied with a different bias voltage as that for the other memory cells.

Abstract: Methods and apparatus for accessing serial presence detect data are provided. For some embodiments, serial presence detect logic is incorporated in memory devices, eliminating the need for a separate serial presence detect component.

Abstract: Systems and methods in accordance with various embodiments can provide for reduced program disturb in non-volatile semiconductor memory. In one embodiment, select memory cells such as those connected to a last word line of a NAND string are programmed using one or more program verify levels or voltages that are different than a corresponding level used to program other cells or word lines. One exemplary embodiment includes using a lower threshold voltage verify level for select physical states when programming the last word line to be programmed for a string during a program operation. Another embodiment includes applying a lower program voltage to program memory cells of the last word line to select physical states. Additional read levels are established for reading the states programmed using lower verify levels in some exemplary implementations.

Abstract: A flash memory device with a reduced access time. The flash memory device executes an error detection and correction operation while encoding or decoding transmission and reception signals with a host apparatus. The flash memory device utilizes a simplified design algorithm and reduces an access time.