Patents Examined by Vicki B Booker
  • Patent number: 10381520
    Abstract: A light emitting device includes a flexible substrate, at least one light emitting element, a sealing resin, an adhesion layer and a support member. The flexible substrate includes a flexible base member and a plurality of wiring portions disposed on one surface of the base member. At least one light emitting element is arranged on a first surface of the flexible substrate and electrically connected to the wiring portions. The sealing resin seals the at least one light emitting element. The adhesion layer and the support member are arranged in this order on a second surface of the flexible substrate different from the first surface of the flexible substrate. The support member has a recess in a region corresponding at least to a region on the first surface where the at least one light emitting element is arranged.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: August 13, 2019
    Assignee: NICHIA CORPORATION
    Inventor: Motokazu Yamada
  • Patent number: 10374131
    Abstract: The invention relates to an optoelectronic component. The component includes a semiconductor layer sequence having an active layer that is designed to emit electromagnetic radiation during operation of the component, at least one current-spreading layer on a radiation outlet surface of the semiconductor layer sequence, wherein the current-spreading layer is connected to a contact structure in an electrically conductive manner by means of an adhesion layer. The adhesion layer comprises a titanium oxide, wherein in the titanium oxide the oxygen has the oxidation state W0, with W0=?2, and the titanium has the oxidation state WT, with 0 <WT<+4.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: August 6, 2019
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventors: Julian Ikonomov, Martin Lemberger, Bjoern Muermann
  • Patent number: 10333012
    Abstract: The method for manufacturing a crystalline silicon substrate for a solar cell includes: forming a texture on the surface of a single-crystalline silicon substrate by bringing an alkali solution and the surface of the single-crystalline silicon substrate into contact with each other; bringing an acidic solution and the surface of the single-crystalline silicon substrate into contact with each other to perform an acid treatment thereon; and then by bringing ozone water and the surface of the single-crystalline silicon substrate into contact with each other to perform an ozone treatment thereon. One aspect of embodiment is that the acidic solution used for the acid treatment is hydrochloric acid. Another aspect of embodiment is that the ozone treatment is performed by immersing the single-crystalline silicon substrate into the ozone water bath.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: June 25, 2019
    Assignee: KANEKA CORPORATION
    Inventors: Toshihiko Uto, Takashi Suezaki, Wataru Yoshida
  • Patent number: 10329482
    Abstract: The invention provides a lighting device including a light source configured to generate light source light and a light converter configured to convert at least part of the light source light into visible converter light. The light converter includes a matrix containing a luminescent material based on derivatives of benzimidazoxanthenoisoquinolinone. The lighting device may include a further luminescent material.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: June 25, 2019
    Assignee: SIGNIFY HOLDING B.V.
    Inventors: Johan Lub, Paulus Albertus Van Hal, Rifat Ata Mustafa Hikmet, Sylvain Loic Jean-Luc Hamon
  • Patent number: 10332869
    Abstract: A power module includes one control IC and a plurality of reverse conducting insulated gate bipolar transistors (RC-IGBTs). The control IC has the functions of a high-voltage IC and a low-voltage IC. The plurality of RC-IGBTs are disposed on three of four sides of the control IC and connected to the control IC through only wires.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: June 25, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Naoki Ikeda, Hisashi Oda, Maki Hasegawa, Hisashi Kawafuji
  • Patent number: 10326090
    Abstract: The present invention relates to a semiconductor composition including an inorganic semiconducting material and an organic binder. The present invention further relates to an electronic device comprising a semiconducting layer consisting of such semiconductor composition.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: June 18, 2019
    Assignee: Merck Patent GmbH
    Inventors: Klaus Bonrad, Matthias Rehahn, Nicole Kolmer-Anderl, Paul Mundt
  • Patent number: 10319847
    Abstract: A method is presented for forming a semiconductor device. The method may include forming a source contact on the semiconductor substrate, forming a drain contact on the semiconductor substrate, and forming a gate structure on the semiconductor substrate between the source and drain contacts, the gate structure including a piezoelectric material having at least one graphene layer.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: June 11, 2019
    Assignee: International Business Machines Corporation
    Inventors: Qing Cao, Ning Li
  • Patent number: 10316135
    Abstract: Four conjugated copolymers with a donor/acceptor architecture including 4,4-dihexadecyl-4H-cyclopenta[1,2-b:5,4-b?]dithiophene as the donor structural unit and benzo[2,1,3]thiodiazole fragments with varying degrees of fluorination have been synthesized and characterized. It has been shown that the HOMO levels were decreased after the fluorine substitution. The field-effect charge carrier mobility was similar for all polymers with less than an order of magnitude difference between different acceptor units.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: June 11, 2019
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Ming Wang, Guillermo C. Bazan
  • Patent number: 10312422
    Abstract: Light emitting devices with improved light extraction efficiency are provided. The light emitting devices have a stack of layers including semiconductor layers comprising an active region. The stack is bonded to a transparent optical element.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: June 4, 2019
    Assignee: Lumileds LLC
    Inventors: Michael D. Camras, Michael R. Krames, Wayne L. Snyder, Frank M. Steranka, Robert C. Taber, John J. Uebbing, Douglas W. Pocius, Troy A. Trottier, Christopher H. Lowery, Gerd O. Mueller, Regina B. Mueller-Mach
  • Patent number: 10297539
    Abstract: The melting of die-bonding solder material is prevented even when soldering a surface-mount component formed using the die-bonding solder material on a printed circuit board using a mounting solder material. The surface-mount component formed using (Sn—Sb)-based solder material having high melting point as the solder material for die pad, the (Sn—Sb)-based solder material containing Cu not more than a predetermined quantity of Cu constituent and a main ingredient thereof being Sn, is soldered on a board terminal portion of a circuit board using (Sn—Ag—Cu—Bi)-based solder material as the mounting solder material with the solder material being applied on the terminal portion. The melting of die-bonding solder material is prevented even at the heating temperature (240 degrees C. or less) of a reflow furnace.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: May 21, 2019
    Assignee: Senju Metal Industry Co., Ltd.
    Inventors: Minoru Ueshima, Minoru Toyoda
  • Patent number: 10294100
    Abstract: A method for manufacturing a gas detector by a micro-electrical-mechanical systems (MEMS) process. The method includes providing a MEMS wafer including a plurality of mutually adjacent units; forming a gas sensing material layer on the MEMS wafer; bonding a structure reinforcing layer and the MEMS wafer through anode bonding; providing an adhesive tape; performing a cutting process to form a gas detection unit; and adhering the gas detection unit on a substrate by the adhesive tape to form a gas detector. The structure reinforcing layer is capable of enhancing the strength of a device and preventing edge collapsing, and hence enhancing the overall yield rate and reducing costs.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: May 21, 2019
    Assignee: Taiwan Carbon Nano Technology Corporation
    Inventors: Yu-Hsuan Liao, Fang-Song Tsai, Ya-Han Wu, Chun-Hsien Tsai, Ting-Chuan Lee, Chun-Jung Tsai
  • Patent number: 10273152
    Abstract: Methods for manufacturing MEMS structures are provided. The method includes forming a first trench and a second trench in a MEMS substrate by performing a main etching process and etching the MEMS substrate through the first trench and the second trench to form a first through hole and an extended second trench by performing a first step of an over-etching process. The method further includes etching the MEMS substrate through the extended second trench to form a second through hole by performing a second step of the over-etching process. In addition, a width of the first trench is greater than a width of the second trench, and a height of the first trench is greater than ¾ of a height of the MEMS substrate, and a height of the second trench is smaller than ? of the MEMS substrate.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Han Meng, Jr-Sheng Chen, Chih-Hsien Hsu, Yu-Pei Chiang, Lin-Ching Huang
  • Patent number: 10192786
    Abstract: A multi-masking process is used to form semiconductor fin arrays having a controlled and variable fin pitch and fin critical dimension within different arrays. A layer of curable silicon nitride is incorporated into a patterning architecture, patterned to form an etch mask, and locally cured to further modify the etch mask geometry. The use of cured and uncured structures facilitate the tuning of the resultant fin geometry.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: January 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Hui Zang, Jinping Liu
  • Patent number: 10192752
    Abstract: Implementations described herein generally relate to processes for the fabrication of semiconductor devices in which a self-assembled monolayer (SAM) is used to achieve selective area deposition. Methods described herein relate to alternating SAM molecule and hydroxyl moiety exposure operations which may be utilized to form SAM layers suitable for blocking deposition of subsequently deposited materials.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: January 29, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Tobin Kaufman-Osborn, Keith Tatseun Wong
  • Patent number: 10163815
    Abstract: A semiconductor wafer contains a plurality of semiconductor die separated by a saw street. A contact pad is formed over an active surface of the semiconductor die. A protective pattern is formed over the active surface of the semiconductor die between the contact pad and saw street of the semiconductor die. The protective pattern includes a segmented metal layer or plurality of parallel segmented metal layers. An insulating layer is formed over the active surface, contact pad, and protective pattern. A portion of the insulating layer is removed to expose the contact pad. The protective pattern reduces erosion of the insulating layer between the contact pad and saw street of the semiconductor die. The protective pattern can be angled at corners of the semiconductor die or follow a contour of the contact pad. The protective pattern can be formed at corners of the semiconductor die.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: December 25, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Xia Feng, Kang Chen, Jianmin Fang
  • Patent number: 10163726
    Abstract: In accordance with some embodiments, a device includes first and second p-type transistors. The first transistor includes a first channel region including a first material of a first fin. The first transistor includes first and second epitaxial source/drain regions each in a respective first recess in the first material and on opposite sides of the first channel region. The first transistor includes a first gate stack on the first channel region. The second transistor includes a second channel region including a second material of a second fin. The second material is a different material from the first material. The second transistor includes third and fourth epitaxial source/drain regions each in a respective second recess in the second material and on opposite sides of the second channel region. The second transistor includes a second gate stack on the second channel region.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Chi-Wen Liu
  • Patent number: 10141195
    Abstract: There is provided a substrate processing method performed on a substrate having a recess formed in a surface thereof, a first silicon-containing film formed on a bottom surface of the recess, a second silicon-containing film formed on both sides of the recess, the method including: depositing a carbon-based deposit on the surface of the substrate; removing the first silicon-containing film by performing a COR (Chemical Oxide Removal) process in which a silicon-containing film is modified to a reaction product using a processing gas, on the substrate; and removing the deposited carbon-based deposit.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: November 27, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Muneyuki Imai, Noriyuki Kobayashi
  • Patent number: 10134647
    Abstract: An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The interconnect structure physically contacts areas of the bond pad that are located outside of a probe contact area that may have been damaged during testing. Insulating material covers the probe contact area and defines openings spaced apart from the probe contact area. The interconnect structure extends through the openings to contact the bond pad.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: November 20, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Owen R. Fay, Kyle K. Kirby, Luke G. England, Jaspreet S. Gandhi
  • Patent number: 10128442
    Abstract: Provided are processes for preparing an electrically doped semiconducting material that includes a [3]-radialene p-dopant. Also provided are processes for preparing an electronic device containing a layer that includes a [3]-radialene p-dopant. The processes may include (i) loading an evaporation source with a [3]-radialene p-dopant and (ii) evaporating the [3]-radialene p-dopant at an elevated temperature and at a reduced pressure. The [3]-radialene p-dopant may be selected from compounds having a structure according to formula (I) herein.
    Type: Grant
    Filed: December 16, 2015
    Date of Patent: November 13, 2018
    Assignee: Novaled GmbH
    Inventors: Markus Hummert, Achim Bruch, Christiane Köhn, Max P. Nüllen, Ulrich Heggemann
  • Patent number: 10128374
    Abstract: A semiconductor device in which sufficient stress can be applied to a channel region due to lattice constant differences.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: November 13, 2018
    Assignee: SONY CORPORATION
    Inventor: Yasushi Tateshita