Abstract: A resist underlayer film-forming composition revealing high reflow properties while applying and heating the composition on a substrate, allowing a flat application on a multi-level substrate thus forming a flat film. The composition includes a copolymer having a repeating structural unit of the following Formula (1) and/or a repeating structural unit of the following Formula (2) and an organic solvent: (in Formulae (1) and (2), R1 is a functional group of Formula (3); in Formula (3), Q1 and Q2 are each independently a hydrogen atom or a C1-5 alkyl group, and * is a dangling bond to an oxygen atom; and in Formula (2), X1 is a C1-50 organic group, and i and j are each independently 0 or 1).

Abstract: In a static electricity protection circuit, an N+ embedded region is provided, extending over an upper surface of a P-type P semiconductor substrate. One N?-semiconductor region, another N?-semiconductor region, and an N? common impurity region are provided in an upward direction from the N+ embedded region. The one N?-semiconductor region and the other N?-semiconductor region are coupled together via the N? common impurity region. A P? impurity region is provided in the upward direction from the one N?-semiconductor region. Another P? impurity region is provided in the upward direction from the other N?-semiconductor region. A diode formed by the one P? impurity region and the one N?-semiconductor region and a diode formed by the other P? impurity region and the other N?-semiconductor region are coupled in opposite directions to each other via the N? common impurity region.

Abstract: Provided is an ink composition capable of improving external quantum efficiency of a photoelectric conversion element. A method for producing an ink composition containing a p-type semiconductor material, an n-type semiconductor material, and a solvent, the method comprising: a step of preparing one or more compositions in which one or both of the p-type semiconductor material and the n-type semiconductor material are dissolved in the solvent; and a step of storing the composition for 4 days or longer to prepare the ink composition. The p-type semiconductor material contains a polymer compound having a donor-acceptor structure.

Abstract: A light emitting module including a circuit board and a lighting emitting device thereon and including first, second, and third LED stacks each including first and second conductivity type semiconductor layers, a first bonding layer between the second and third LED stacks, a second bonding layer between the first and second LED stacks, a first planarization layer between the second bonding layer and the third LED stack, a second planarization layer on the first LED stack, a lower conductive material extending along sides of the first planarization layer, the second LED stack, the first bonding layer, and electrically connected to the first conductivity type semiconductor layers of each LED stack, respectively, and an upper conductive material between the circuit board and the lower conductive material.

Abstract: An organic light-emitting display device includes a first substrate having sub-pixel areas, each sub-pixel area having a light-emitting area and a non-light-emitting area; thin-film transistors respectively in non-light-emitting areas of the sub-pixel areas; a first planarization layer in the sub-pixel areas while covering the thin-film transistors; organic light-emitting elements on the first planarization layer and in light-emitting areas of the sub-pixel areas; a liquid crystal layer on the organic light-emitting elements and in the sub-pixel areas and in an area between the sub-pixel areas; and a second substrate on the liquid crystal layer. Liquid crystal molecules of the liquid crystal layer in the light-emitting areas are in a hybrid alignment. In the hybrid alignment, an alignment of the liquid crystal molecules gradually changes from a horizontal alignment to a vertical alignment. Liquid crystal molecules of the liquid crystal layer in the non-light-emitting areas are in a tilted alignment.

Abstract: A semiconductor packaging method, a semiconductor assembly and an electronic device comprising the semiconductor assembly are described herein. The semiconductor packaging method comprises providing at least one semiconductor device and a carrier board. A plurality of first alignment solder parts are formed on an active surface of each semiconductor device in addition to connection terminals. A plurality of second alignment solder parts are formed on a surface of the carrier board.

Abstract: A micro light-emitting device includes a support structure with a cavity and at least one micro light-emitting element that includes a semiconductor structure accommodated by the cavity, at least one bridge connection member disposed on the semiconductor structure to interconnect the semiconductor structure and the support structure, and a protruding contact member disposed on at least one of the semiconductor structure and the bridge connection member and protruding therefrom to be configured to contact with a transfer means. The device is configured to contact with the transfer means at the protruding contact member of the element. A transfer method using the device is also disclosed.

Abstract: A stacked light emitting device includes a first LED stack, a second LED stack disposed under the first LED stack, a third LED stack disposed under the second LED stack, and a plurality of pads disposed over the first LED stack. Each of the first, second, and third LED stacks has a light generation region and a peripheral region disposed around the light generation region. The plurality of pads is disposed on the peripheral region of the first LED stack.

Abstract: An array substrate and a method of manufacturing the same are provided. The array substrate includes a substrate, a thin film transistor, a first passivation layer, an organic film layer, a common electrode, a second passivation layer and a pixel electrode layer. The organic film layer includes a first via. The common electrode covers the pixel area and includes a second via and a sloped wall surrounding the second via. The second via is connected with the first via, and a gap is located between the bottom edge of the sloped wall and the top edge of the first via. The second passivation layer includes a third via communicating with the second via. The pixel electrode layer is arranged on the second passivation layer and is connected with the second metal layer through the first via, the second via, and the third via.

Abstract: A chip includes a substrate having a first surface and a second surface opposite the first surface, and an integrated circuit mounted on a landing zone on the first surface of the substrate. The chip also includes contacts provided about the first surface in the peripheral region, and wire-bonds providing electrical connections between the integrated circuit and the contacts. The chip further includes solder ball connections provided in the peripheral region on the second surface, and connections provided in the substrate for connecting the electrical contacts on the first surface with the solder ball connections on the second surface. The substrate includes at least one conductive track routed through the landing zone region of the substrate, and the chip is configured such that an alteration in the at least one conductive track prevents operation of the integrated circuit.

Abstract: The present disclosure provides a flexible display panel, which includes a substrate, a plurality of hollow regions, a plurality of display units, a plurality of wire structures, and a plurality of spacers. The substrate is defined as a plurality of island regions and a plurality of bridge regions. Each of the hollow regions is surrounded by four adjacent of the island regions and four adjacent of the bridge regions. The display units are respectively disposed on the island regions of the substrate. The wire structures are respectively disposed on the bridge regions and electrically connected to the display units. Each of the wire structures includes at least one wire layer including at least one wire disposed on the substrate. The spacers are disposed on and in contact with the substrate, and respectively surround the hollow regions, and separated from the wire structures to control etching sizing.

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region; a first MTJ on the MTJ region; a first metal interconnection on the logic region; and a cap layer extending from a sidewall of the first MTJ to a sidewall of the first metal interconnection. Preferably, the cap layer on the MTJ region and the cap layer on the logic region comprise different thicknesses.

Abstract: A display device includes: a gate line including a gate line portion; a data line; a transistor including a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode; and a connecting member disposed between the data line and the source electrode, connected to the data line and the source electrode to cross a gate electrode edge of the gate electrode. A connecting portion where a data line edge and a connecting member edge are connected to each other does not overlap the gate line and the gate electrode in a plan view. The data line includes a first data line portion crossing the gate line and a second data line portion connected to the first data line portion and does not overlap the gate line in the plan view.

Abstract: A semiconductor device includes a region of semiconductor material of a first conductivity type. A body region of a second conductivity type is in the region of semiconductor material. The body region includes a first segment with a first peak dopant concentration, and a second segment laterally adjacent to the first segment with a second peak dopant concentration. A source region of the first conductivity type is in the first segment but not in at least part of the second segment. An insulated gate electrode adjoins the first segment and is configured to provide a first channel region in the first segment, adjoins the second segment and is configured to provide a second channel region in the second segment, and adjoins the source region. During a linear mode of operation, current flows first in the second segment but not in the first segment to reduce the likelihood of thermal runaway.

Abstract: A micro light emitting diode display includes a substrate, an electrode layer disposed on the substrate, a micro light emitting diode device disposed on the electrode layer, a metal layer disposed on the substrate and connected to the electrode layer, and first and second encapsulation layers. The substrate has an air passage extending to opposite surfaces thereof. The first encapsulation layer wraps the micro light emitting diode device. The second encapsulation layer covers the metal layer and has a material different from that of the first encapsulation layer. The metal layer has a visible area in a display region of the substrate that is not covered by the micro light emitting diode device. A part of the visible area is covered by the second encapsulation layer, and a proportion of the part to the visible area is equal to or greater than 60%.

Abstract: A curved display module is provided, which includes a stretchable display panel and a first support layer. The stretchable display panel includes a plurality of pixel islands and a connection bridge configured for connecting adjacent two of the pixel islands. A stretching degree of the connection bridge in the first stretching area is less than a stretching degree of the connection bridge in the second stretching area. A four-sided curved 3D stereo display panel is realized by the present disclosure, and the risk of distortion and deformation of the display panel during stretching is reduced as well.

Abstract: A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor fin. The semiconductor structure also includes a first nanowire vertically overlapping a top surface of the semiconductor fin, a second nanowire vertically overlapping the first nanowire, and a third nanowire vertically overlapping the second nanowire. The semiconductor structure further includes a gate wrapping around the first nanowire, the second nanowire, and the third nanowire. A first portion of the gate vertically sandwiched between the first nanowire and the second nanowire is greater than a second portion of the gate vertically sandwiched between the second nanowire and the third nanowire.

Abstract: The pixel structure includes a plurality of blue pixel sets, a plurality of yellow pixel sets, a first film filter, and a second film filter; the blue pixel set is composed of a plurality of blue sub-pixels arranged in a longitudinal direction, and the yellow pixel set is composed of a plurality of yellow sub-pixels arranged in the longitudinal direction; one blue pixel group and one yellow pixel group adjacent to each other in a horizontal direction constitute a hybrid pixel group, and a plurality of hybrid pixel sets are arranged in a transverse direction; in the hybrid pixel group, each blue sub-pixel is adjacent to at least two of the plurality of yellow sub-pixels, and the blue sub-pixel and at least two adjacent yellow sub-pixels constitute one pixel unit.

Abstract: A display device includes a display area, a frame area around the display area, and a contact area between the display area and the frame area. In the display area is there provided a light-emitting element layer including an anode, a functional layer, a cathode, and a pixel bank covering an edge of the anode. The cathode is electrically connected to a metal film in the contact area. An insular TEG pattern is provided in the contact area.