Patents Examined by Victor A. Mandala
  • Patent number: 11075227
    Abstract: A display substrate, a method for manufacturing the display substrate, and a display device are provided. The display substrate includes a display area and a fanout area at the periphery of the display area. The fanout area includes a data line layer, a first power line layer, and at least two insulation layers between the data line layer and the first power line layer. In a direction perpendicular to a base substrate of the display substrate, the first power line layer overlaps the data line layer. At least one of the at least two insulation layers includes a portion which insulates the first power line layer and the data line layer from each other.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: July 27, 2021
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jun Wang, Dongfang Wang, Haitao Wang, Guangyao Li, Yingbin Hu, Yang Zhang, Qinghe Wang, Liangchen Yan
  • Patent number: 11069744
    Abstract: Embodiments of the invention are directed to a method and resulting structures for a steep-switch vertical field effect transistor (SS-VFET). In a non-limiting embodiment of the invention, a semiconductor fin is formed vertically extending from a bottom source or drain region of a substrate. A top source or drain region is formed on a surface of the semiconductor fin and a top metallization layer is formed on the top source or drain region. A bi-stable resistive system is formed on the top metallization layer. The bi-stable resistive system includes an insulator-to-metal transition material or a threshold-switching selector. The SS-VFET provides a subthreshold switching slope of less than 60 millivolts per decade.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: July 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel Chanemougame, Julien Frougier, Nicolas J. Loubet, Ruilong Xie
  • Patent number: 11063213
    Abstract: A method includes depositing a bottom electrode layer, a resistance switching element layer, and a top electrode layer over a first dielectric layer; etching the top electrode layer and the resistance switching element layer to form a resistance switching element over the bottom electrode layer and a top electrode over the resistance switching element; depositing a metal-containing compound layer over the top electrode, the resistance switching element, and the bottom electrode layer; and etching the metal-containing compound layer and the bottom electrode layer to form a bottom electrode over the first dielectric layer.
    Type: Grant
    Filed: October 26, 2019
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Wei Lu, Hsi-Wen Tien, Wei-Hao Liao, David Dai, Chung-Ju Lee
  • Patent number: 11064615
    Abstract: A microelectronic device includes a die less than 300 microns thick, and an interface tile. Die attach leads on the interface tile are electrically coupled to die terminals on the die through interface bonds. The microelectronic device includes an interposer between the die and the interface tile. Lateral perimeters of the die, the interposer, and the interface tile are aligned with each other. The microelectronic device may be formed by forming the interface bonds and an interposer layer, while the die is part of a wafer and the interface tile is part of an interface lamina. Kerfs are formed through the interface lamina, through the interposer, and partway through the wafer, around a lateral perimeter of the die. Material is subsequently removed at a back surface of the die to the kerfs, so that a thickness of the die is less than 300 microns.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: July 13, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Sreenivasan K Koduri
  • Patent number: 11063026
    Abstract: A method of manufacturing a display module is provided. The method may include providing a substrate including a pixel region on which a plurality of electrodes are disposed and a peripheral region that is a region other than the pixel region on the substrate; forming an adhesive layer on the pixel region of the substrate; transferring a plurality of micro light emitting diodes (LEDs) onto the adhesive layer; pre-curing the adhesive layer to shift the adhesive layer on the pixel region to the peripheral region; and bonding the plurality of micro LEDs to the plurality of electrodes.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: July 13, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Eunhye Kim, Doyoung Kwag, Byungchul Kim, Sangmoo Park, Minsub Oh, Dongyeob Lee, Yoonsuk Lee
  • Patent number: 11056584
    Abstract: In a semiconductor device having an active region and an inactive region, the active region includes a channel forming layer with a heterojunction structure having first and second semiconductor layers, a gate structure portion having a MOS gate electrode, a source electrode and a drain electrode disposed on the second semiconductor layer with the gate structure portion interposed therebetween, a third semiconductor layer disposed at a position away from the drain electrode between the gate structure portion and the drain electrode and not doped with an impurity, a p-type fourth semiconductor layer disposed on the third semiconductor layer, and a junction gate electrode brought into contact with the fourth semiconductor layer. The junction gate electrode is electrically connected to the source electrode to have a same potential as a potential of the source electrode, and is disposed only in the active region.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: July 6, 2021
    Assignee: DENSO CORPORATION
    Inventors: Kensuke Hata, Shinichi Hoshi, Hideo Matsuki, Youngshin Eum, Shigeki Takahashi
  • Patent number: 11056630
    Abstract: A display module includes a glass substrate having a front surface and a back surface opposite to the front surface; a TFT layer; LEDs mounted on the TFT layer; and a plurality of side wirings formed at intervals in an edge area of the glass substrate, and the edge area includes a first area corresponding to a side surface of the glass substrate, a second area adjacent to the side surface, and a third area adjacent to the side surface, and a first chamfered surface formed by chamfering a corner at which the first area and the second area meet, and a second chamfered surface formed by chamfering a corner at which the first area and the third area meet, and each of the plurality of side wirings is disposed along the second area, the first chamfered surface, the first area, the second chamfered surface, and the third area.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: July 6, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Soonmin Hong, Gyuhwa Kim, Jeonggen Yoon, Tackmo Lee, Gyun Heo, Youngjun Moon, Kyungwoon Jang
  • Patent number: 11056342
    Abstract: A method of fabricating a semiconductor device includes forming a protective layer on a portion of the semiconductor body that is not to be silicided. The protective layer includes a silicon oxide layer and a silicon nitride layer over the silicon oxide layer. At least a portion of the silicon nitride layer of the protective layer is removed. A silicided portion of the semiconductor body is laterally spaced from the protective layer. The siliciding is performed by an ion sputtering in a plasma environment on both the silicided portion of the semiconductor body and the portion of the semiconductor body that is not to be silicided.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: July 6, 2021
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Denis Monnier, Olivier Gonnard
  • Patent number: 11049785
    Abstract: In a semiconductor device, it is preferable to suppress a variation in characteristics of a temperature sensor. The semiconductor device is provided that includes a semiconductor substrate having a first conductivity type drift region, a transistor section provided in the semiconductor substrate, a diode section provided in the semiconductor substrate, a second conductivity type well region exposed at an upper surface of the semiconductor substrate, a temperature sensing unit that is adjacent to the diode section in top view and is provided above the well region, and an upper lifetime control region that is provided in the diode section, at the upper surface side of the semiconductor substrate, and in a region not overlapping with the temperature sensing unit in top view.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: June 29, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Motoyoshi Kubouchi, Soichi Yoshida
  • Patent number: 11049774
    Abstract: A method includes forming an epitaxy semiconductor layer over a semiconductor substrate, and etching the epitaxy semiconductor layer and the semiconductor substrate to form a semiconductor strip, which includes an upper portion acting as a mandrel, and a lower portion under the mandrel. The upper portion is a remaining portion of the epitaxy semiconductor layer, and the lower portion is a remaining portion of the semiconductor substrate. The method further includes growing a first semiconductor fin starting from a first sidewall of the mandrel, growing a second semiconductor fin starting from a second sidewall of the mandrel. The first sidewall and the second sidewall are opposite sidewalls of the mandrel. A first transistor is formed based on the first semiconductor fin. A second transistor is formed based on the second semiconductor fin.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: June 29, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Hsun Wang, Shih-Cheng Chen, Chun-Hsiung Lin, Chih-Hao Wang
  • Patent number: 11049998
    Abstract: An electroluminescent display panel and a display device are provided. In the embodiments of the disclosure, a photosensitive device is arranged in the photosensitive device arranging region. The extending line of at least one line is arranged in the photosensitive device arranging region so that the orthographic projection of the extending line on the light-emitting surface of the electroluminescent display panel overlaps with the first pixels in the first and second specific pixel groups in the photosensitive device arranging area; the first and second specific pixel groups include respective first pixels located in first straight lines of the second pixels correspondingly connected to two adjacent signal lines, the first and second specific pixel groups are adjacent in the second direction, and the first straight lines extend in the first direction.
    Type: Grant
    Filed: December 28, 2019
    Date of Patent: June 29, 2021
    Assignee: WUHAN TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Yangzhao Ma, Yuejun Tang, Ruiyuan Zhou
  • Patent number: 11050018
    Abstract: A memory device includes a bottom electrode, a resistance switching element, a top electrode, a first spacer, and a metal-containing compound layer. The resistance switching element is over the bottom electrode. The top electrode is over the resistance switching element. The first spacer is disposed along a sidewall of the resistance switching element. The metal-containing compound layer is disposed along a sidewall of the first spacer, in which the first spacer is between the metal-containing compound layer and the resistance switching element.
    Type: Grant
    Filed: October 26, 2019
    Date of Patent: June 29, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Wei Lu, Hsi-Wen Tien, Wei-Hao Liao, David Dai, Chung-Ju Lee
  • Patent number: 11049802
    Abstract: A package includes a first layer of molding material, a first metallization layer on the first layer of molding material, a second layer of molding material on the first metallization layer and the first layer of molding material, a second metallization layer on the second layer of molding material, through vias within the second layer of molding material, the through vias extending from the first metallization layer to the second metallization layer, integrated passive devices within the second layer of molding material, a redistribution structure electrically on the second metallization layer and the second layer of molding material, the redistribution structure connected to the through vias and the integrated passive devices, and at least one semiconductor device on the redistribution structure, the at least one semiconductor device connected to the redistribution structure.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: June 29, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun Yi Wu, Chen-Hua Yu
  • Patent number: 11043553
    Abstract: An integrated circuit device includes a lower electrode, an upper electrode, and a dielectric layer structure between the lower electrode and the upper electrode, the dielectric layer structure including a first surface facing the lower electrode and a second surface facing the upper electrode. The dielectric layer structure includes a first dielectric layer including a first dielectric material and a plurality of grains extending from the first surface to the second surface and a second dielectric layer including a second dielectric material and surrounding a portion of a sidewall of each of the plurality of grains of the first dielectric layer in a level lower than the second surface. The second dielectric material includes a material having bandgap energy which is higher than bandgap energy of the first dielectric material.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: June 22, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Youn-soo Kim, Seung-min Ryu, Chang-su Woo, Hyung-suk Jung, Kyu-ho Cho, Youn-joung Cho
  • Patent number: 11038067
    Abstract: A sensor for measuring mechanical stress in a layered metallization structure such as the back end of line portion of an integrated circuit die is provided. The sensor operates as a field effect transistor comprising a gate electrode, gate dielectric, channel and source and drain electrodes, wherein the gate electrode is a conductor of a first metallization level and the source and drain electrodes are two interconnect vias, connecting the channel to respective conductors in an adjacent level. At least one of the interconnect vias is formed of a material whereof the electrical resistance is sensitive to mechanical stress in the direction of the via. The sensitivity of the electrical resistance to the mechanical stress is sufficient to facilitate measurement of the stress by reading out the drain current of the transistor. The sensor thereby allows monitoring of stress in the BEOL prior to cracking.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: June 15, 2021
    Assignee: IMEC vzw
    Inventors: Gaspard Hiblot, Luka Kljucar
  • Patent number: 11031345
    Abstract: Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a substrate having a core layer disposed between a first dielectric layer and a second dielectric layer, a die disposed in a cavity of the core layer, and an encapsulant disposed in the cavity between the die and a sidewall of the cavity. The package further includes a first patterned conductive layer disposed within the first dielectric layer, a device disposed on an outer surface of the first dielectric layer such that the first patterned conductive layer is between the device and the core layer, a second patterned conductive layer disposed within the second dielectric layer, and a conductive pad disposed on an outer surface of the second dielectric layer such that the second patterned conductive layer is between the conductive pad and the core layer.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: June 8, 2021
    Assignee: Medtronic, Inc.
    Inventors: Chunho Kim, Mark R. Boone, Randolph E. Crutchfield
  • Patent number: 11031328
    Abstract: A semiconductor package includes: an interposer substrate including a core substrate and a connection structure, the core substrate having a cavity and having through-vias connecting upper and lower surfaces thereof, and the connection structure including an insulating member on the upper surface and a redistribution layer on the insulating member; a semiconductor chip on an upper surface of the connection structure and including connection pads connected to the redistribution layer; a passive component accommodated in the cavity; a first insulating layer disposed between the core substrate and the connection structure; a first wiring layer on the first insulating layer and connecting the through-vias and the passive component to the redistribution layer; a second insulating layer on the lower surface of the core substrate; and a second wiring layer on a lower surface of the second insulating layer and connected to the through-vias.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: June 8, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junghyun Cho, Youngsik Hur, Youngkwan Lee, Jongrok Kim
  • Patent number: 11031250
    Abstract: A semiconductor device and method of formation thereof. The semiconductor device includes a portion of a first material that abuts a portion of a second material and surrounds at least a portion of a semiconductor component. The first material has a first composition and a first index of refraction and is of a same type of material as the second material. The second material has a second composition and a second index of refraction. An opening in the first material exposes a portion of the semiconductor component.
    Type: Grant
    Filed: November 29, 2018
    Date of Patent: June 8, 2021
    Assignee: International Business Machines Corporation
    Inventors: Mona A. Ebrish, Michael Rizzolo, Son Nguyen, Raghuveer R. Patlolla, Donald F. Canaperi
  • Patent number: 11024736
    Abstract: A transistor comprises a top source/drain region, a bottom source/drain region, a channel region vertically between the top and bottom source/drain regions, and a gate operatively laterally-adjacent the channel region. At least one of the top source/drain region, the bottom source/drain region, and the channel region are crystalline. All crystal grains within the at least one of the top source/drain region, the bottom source/drain region, and the channel region have average crystal sizes within 0.064 ?m3 of one another. Other embodiments, including methods, are disclosed.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: June 1, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Hung-Wei Liu, Sameer Chhajed, Jeffery B. Hull, Anish A. Khandekar
  • Patent number: 11024697
    Abstract: A display apparatus includes a base substrate that includes a display area in which pixels are formed and a peripheral area that is a non-display area that surrounds the display area, a first conductive pattern layer disposed on the base substrate, a first insulating layer disposed on the first conductive pattern layer, a second conductive pattern layer disposed on the first insulating layer, a second insulating layer disposed on the second conductive pattern layer, and a third conductive pattern layer disposed on the second insulating layer. The peripheral area includes a first wiring area and a circuit area.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: June 1, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Junhyun Park, Dongwoo Kim, Sungjae Moon, Kangmoon Jo