Patents Examined by Victor A. Mandala
  • Patent number: 11990579
    Abstract: A display device includes a substrate and pixels. The substrate includes: a display area including pixel areas, each including a first area and a second area; and a non-display area enclosing at least one side of the display area. The pixels are disposed on the pixel areas, each pixel including light emitting elements. Each pixel further includes: a pixel circuit part disposed on the first area and including at least one transistor and at least one capacitor; and a display element part disposed on the second area and including an emission area to emit light. Each of the pixel circuit part and the display element part has a multi-layer structure including one or more conductive layers and one or more insulating layers. At least one layer of the pixel circuit part and at least one layer of the display element part are disposed in a same layer.
    Type: Grant
    Filed: December 23, 2022
    Date of Patent: May 21, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kyung Bae Kim, Mee Hye Jung, Chong Chul Chai
  • Patent number: 11984365
    Abstract: A high atomic number material is applied to one or more surfaces of a semiconductor structure of a wafer. The one or more surfaces are at a depth different from a depth of a surface of the wafer. An electron beam is scanned over the semiconductor structure to cause a backscattered electron signal to be collected at a collector. A profile scan of the semiconductor structure is generated based on an intensity of the backscattered electron signal, at the collector, resulting from the high atomic number material. The high atomic number material increases the intensity of the backscattered electron signal for the one or more surfaces of the semiconductor structure such that contrast in the profile scan is increased. The increased contrast of the profile scan enables accurate critical dimension measurements of the semiconductor structure.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: May 14, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Pei-Hsuan Lee, Hung-Ming Chen, Kuang-Shing Chen, Yu-Hsiang Cheng, Xiaomeng Chen
  • Patent number: 11984375
    Abstract: In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.
    Type: Grant
    Filed: April 18, 2023
    Date of Patent: May 14, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Hsun Chen, Yu-Ling Tsai, Jiun Yi Wu, Chien-Hsun Lee, Chung-Shi Liu
  • Patent number: 11978842
    Abstract: A method of manufacturing an electronics assembly includes forming a base layer, forming a first thermally and electrically conductive intermediate layer onto the base layer using an additive manufacturing process, placing an electronics component onto the first thermally and electrically conductive intermediate layer, the electronics component comprising a plurality of vias, and forming a second thermally and electrically conductive intermediate layer over the first thermally and electrically conductive intermediate layer and over at least a portion of the electronics component using an additive manufacturing process, wherein a material of the second thermally and electrically conductive intermediate layer extends through the vias to contact the first thermally and electrically conductive intermediate layer and the vias, thereby forming a bond therebetween.
    Type: Grant
    Filed: January 17, 2023
    Date of Patent: May 7, 2024
    Assignee: Ford Global Technologies, LLC
    Inventors: Stuart C. Salter, David Brian Glickman, Paul Kenneth Dellock, Richard Gall, Harold P. Sears
  • Patent number: 11978625
    Abstract: Embodiments of the disclosure include methods of forming a film comprising conformally depositing a first film on a substrate; treating the first film with a first plasma to form a second film; treating the second film with a second plasma to form a third film; and selectively removing the first film, a portion of the second film, and the third film.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: May 7, 2024
    Assignee: Applied Materials, Inc.
    Inventor: Joseph AuBuchon
  • Patent number: 11967670
    Abstract: A display device includes a first pixel and a second pixel adjacent to each other in a first direction, first voltage wires disposed in the first pixel and the second pixel in a second direction, a second wire disposed along a boundary between the first pixel and the second pixel in the second direction, first electrodes disposed between the first voltage wires and the second wire in the first pixel an the second pixel, a second electrode disposed between and spaced apart from the first electrodes in the first pixel and the second pixel, and light-emitting elements disposed at each of the first pixel and the second pixel and disposed on the first electrodes and the second electrode, wherein the first voltage wires, the first electrodes, and the light-emitting elements are symmetric with respect to the second wire.
    Type: Grant
    Filed: February 17, 2021
    Date of Patent: April 23, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: An Na Ryu, Sung Hoon Kim, Sang Ho Park
  • Patent number: 11967546
    Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.
    Type: Grant
    Filed: July 21, 2022
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Yun Hou, Hsien-Pin Hu, Sao-Ling Chiu, Wen-Hsin Wei, Ping-Kang Huang, Chih-Ta Shen, Szu-Wei Lu, Ying-Ching Shih, Wen-Chih Chiou, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 11967528
    Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.
    Type: Grant
    Filed: April 26, 2023
    Date of Patent: April 23, 2024
    Assignee: Apple Inc.
    Inventors: Vidhya Ramachandran, Jun Zhai, Chonghua Zhong, Kunzhong Hu, Shawn Searles, Joseph T. DiBene, II, Mengzhi Pang
  • Patent number: 11968832
    Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the disclosed method comprises forming a plurality of dielectric stacks stacked on one another over a substrate to create a multiple-stack staircase structure. Each one of the plurality of dielectric stacks comprises a plurality of dielectric pairs arranged along a direction perpendicular to a top surface of the substrate. The method further comprises forming a filling structure that surrounds the multiple-stack staircase structure, forming a semiconductor channel extending through the multiple-staircase structure, wherein the semiconductor channel comprises unaligned sidewall surfaces, and forming a supporting pillar extending through at least one of the multiple-staircase structure and the filling structure, wherein the supporting pillar comprises aligned sidewall surfaces.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: April 23, 2024
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jun Liu, Zongliang Huo, Li Hong Xiao, Zhenyu Lu, Qian Tao, Yushi Hu, Sizhe Li, Zhao Hui Tang, Yu Ting Zhou, Zhaosong Li
  • Patent number: 11967390
    Abstract: An apparatus includes a substrate; circuit components disposed on the substrate; and a location identifier layer over the circuit, wherein the location identifier layer includes one or more section labels for representing physical locations of the circuit components within the apparatus.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: April 23, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Itamar Lavy, Chunhao Wang, Wesley B. Butler
  • Patent number: 11961893
    Abstract: Improved conductive contacts, methods for forming the same, and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a first interlayer dielectric (ILD) layer over a transistor structure; a first contact extending through the first ILD layer, the first contact being electrically coupled with a first source/drain region of the transistor structure, a top surface of the first contact being convex, and the top surface of the first contact being disposed below a top surface of the first ILD layer; a second ILD layer over the first ILD layer and the first contact; and a second contact extending through the second ILD layer, the second contact being electrically coupled with the first contact.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Te-Chih Hsiung, Jyun-De Wu, Yi-Chen Wang, Yi-Chun Chang, Yuan-Tien Tu
  • Patent number: 11963377
    Abstract: A light-emitting diode display including a substrate having a driving circuitry and a plurality of light emitting diode structures disposed on the substrate. Each light-emitting diode structure has a light emitting diode with a light emission zone having a planar portion, and a pigmentless light extraction layer of a UV-cured ink disposed over the light-emitting diode. The light extraction layer has a gradient in index of refraction along an axis normal to the planar portion, and the index of refraction of the light extraction layer decreases with distance from the planar portion.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: April 16, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Gang Yu, Chung-Chia Chen, Wan-Yu Lin, Hyunsung Bang, Lisong Xu, Byung Sung Kwak, Robert Jan Visser
  • Patent number: 11961867
    Abstract: Various aspects of the present disclosure provide a semiconductor device, for example comprising a finger print sensor, and a method for manufacturing thereof. Various aspects of the present disclosure may, for example, provide an ultra-slim finger print sensor having a thickness of 500 ?m or less that does not include a separate printed circuit board (PCB), and a method for manufacturing thereof.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: April 16, 2024
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Jin Young Kim, No Sun Park, Yoon Joo Kim, Seung Jae Lee, Se Woong Cha, Sung Kyu Kim, Ju Hoon Yoon
  • Patent number: 11961871
    Abstract: A display device with high resolution is provided. Manufacturing cost of a display device using a micro LED as a display element is reduced. The display device includes a substrate, a plurality of transistors, and a plurality of light-emitting diodes. The plurality of light-emitting diodes are provided in a matrix over the substrate. Each of the plurality of transistors are electrically connected to at least one of the plurality of light-emitting diodes. The plurality of light-emitting diodes are positioned closer to the substrate than the plurality of transistors are. The plurality of light-emitting diodes emit light to the opposite side of the substrate.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: April 16, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Kusunoki, Shingo Eguchi, Yosuke Tsukamoto, Kazunori Watanabe, Kouhei Toyotaka
  • Patent number: 11955383
    Abstract: A semiconductor device manufacturing method includes: providing a semiconductor base; patterning the first medium layer to form a groove extending along the base in the base; forming a first auxiliary layer and a first metal layer sequentially in the groove, where the first metal layer is located on the side of the first auxiliary layer towards the first medium layer; thinning the base on the second surface of the base to expose the first auxiliary layer; removing the first auxiliary layer to form a first opening; and forming a second metal layer on the second surface of the base, where the second metal layer fills the first opening.
    Type: Grant
    Filed: November 7, 2021
    Date of Patent: April 9, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Jie Liu, Bin Yang, Zhan Ying
  • Patent number: 11949056
    Abstract: The light emitting diode packaging structure includes a flexible substrate, a first adhesive layer, micro light emitting elements, a conductive pad, a redistribution layer, and an electrode pad. The first adhesive layer is disposed on the flexible substrate. The micro light emitting elements are disposed on the first adhesive layer and have a first surface facing to the first adhesive layer and an opposing second surface. The micro light emitting elements include a red micro light emitting element, a blue micro light emitting element, and a green micro light emitting element. The conductive pad is disposed on the second surface of the micro light emitting element. The redistribution layer covers the micro light emitting elements and the conductive pad. The electrode pad is disposed on the redistribution layer and is electrically connected to the circuit layer. A thickness of the flexible substrate is less than 100 um.
    Type: Grant
    Filed: April 20, 2023
    Date of Patent: April 2, 2024
    Assignee: Lextar Electronics Corporation
    Inventors: Chih-Hao Lin, Jo-Hsiang Chen, Shih-Lun Lai, Min-Che Tsai, Jian-Chin Liang
  • Patent number: 11949021
    Abstract: A semiconductor device having a structure which can prevent a decrease in electrical characteristics due to miniaturization is provided. The semiconductor device includes, over an insulating surface, a stack in which a first oxide semiconductor layer and a second oxide semiconductor layer are sequentially formed, and a third oxide semiconductor layer covering part of a surface of the stack. The third oxide semiconductor layer includes a first layer in contact with the stack and a second layer over the first layer. The first layer includes a microcrystalline layer, and the second layer includes a crystalline layer in which c-axes are aligned in a direction perpendicular to a surface of the first layer.
    Type: Grant
    Filed: April 11, 2023
    Date of Patent: April 2, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura, Hideomi Suzawa
  • Patent number: 11942454
    Abstract: A package includes a first die, a second die, and an encapsulant. The first die has a first interconnection structure, and the first interconnection structure includes a first capacitor embedded therein. The second die has a second interconnection structure, and the second interconnection structure includes a second capacitor embedded therein. The first interconnection structure faces the second interconnection structure. The second die is stacked on the first die. The first capacitor is electrically connected to the second capacitor. The encapsulant laterally encapsulates the second die.
    Type: Grant
    Filed: May 9, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen, Ming-Fa Chen
  • Patent number: 11942543
    Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chou Lin, Yi-Cheng Chiu, Karthick Murukesan, Yi-Min Chen, Shiuan-Jeng Lin, Wen-Chih Chiang, Chen-Chien Chang, Chih-Yuan Chan, Kuo-Ming Wu, Chun-Lin Tsai
  • Patent number: 11942396
    Abstract: A heterogeneous integration semiconductor package structure including a heat dissipation assembly, multiple chips, a package assembly, multiple connectors and a circuit substrate is provided. The heat dissipation assembly has a connection surface and includes a two-phase flow heat dissipation device and a first redistribution structure layer embedded in the connection surface. The chips are disposed on the connection surface of the heat dissipation assembly and electrically connected to the first redistribution structure layer. The package assembly surrounds the chips and includes a second redistribution structure layer disposed on a lower surface and multiple conductive vias electrically connected to the first redistribution structure layer and the second redistribution structure layer. The connectors are disposed on the package assembly and electrically connected to the second redistribution structure layer.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: March 26, 2024
    Assignee: Industrial Technology Research Institute
    Inventors: Heng-Chieh Chien, Shu-Jung Yang, Yu-Min Lin, Chih-Yao Wang, Yu-Lin Chao