Abstract: A fan-out semiconductor package includes a first connection structure having first and second surfaces, a first semiconductor chip disposed on the first surface, a first encapsulant disposed on the first surface and covering at least a portion of the first semiconductor chip, a second semiconductor chip disposed on the second surface, one or more first metal members disposed on the second surface, one or more second metal members disposed on the second surface, a second encapsulant disposed on the second surface and respectively covering at least portions of the second semiconductor chip and the first and second metal members, and a second connection structure disposed on an opposite side of a side of the second encapsulant, on which the first connection structure is disposed.

Abstract: In a semiconductor device, it is preferable to suppress a variation in characteristics of a temperature sensor. The semiconductor device is provided that includes a semiconductor substrate having a first conductivity type drift region, a transistor section provided in the semiconductor substrate, a diode section provided in the semiconductor substrate, a second conductivity type well region exposed at an upper surface of the semiconductor substrate, a temperature sensing unit that is adjacent to the diode section in top view and is provided above the well region, and an upper lifetime control region that is provided in the diode section, at the upper surface side of the semiconductor substrate, and in a region not overlapping with the temperature sensing unit in top view.

Abstract: In one example, an electronic device includes a substrate having a conductive structure. The conductive structure includes a substrate inward terminal at a first side of the substrate and a substrate outward terminal at a second side of the substrate. The substrate includes a dielectric structure with a first opening is at the second side. An electronic component is at the first side of the substrate and is electrically coupled to the substrate inward terminal, and an encapsulant encapsulates the electronic component. The substrate outward terminal comprises one of a multi-via terminal or a multi-stage via. The multi-via terminal includes pad conductive vias in the first opening a pad dielectric via interposed between the pad conductive vias in the first opening and a conductor comprising a conductor top side with micro dimples over the pad conductive vias and the pad dielectric via.

Abstract: A first lead wiring line and a second lead wiring line intersecting a bending portion of a frame region overlap each other and are electrically connected to each other, and in a first resin layer interposed between the first lead wiring line and the second lead wiring line, a plurality of tapered holes are formed and overlap the first lead wiring line and the second lead wiring line.

Abstract: A package includes a first layer of molding material, a first metallization layer on the first layer of molding material, a second layer of molding material on the first metallization layer and the first layer of molding material, a second metallization layer on the second layer of molding material, through vias within the second layer of molding material, the through vias extending from the first metallization layer to the second metallization layer, integrated passive devices within the second layer of molding material, a redistribution structure electrically on the second metallization layer and the second layer of molding material, the redistribution structure connected to the through vias and the integrated passive devices, and at least one semiconductor device on the redistribution structure, the at least one semiconductor device connected to the redistribution structure.

Abstract: An image sensor device is provided. The image sensor device includes a substrate having a front surface, a back surface, and a light-sensing region. The image sensor device includes a first isolation structure extending from the front surface into the substrate. The first isolation structure surrounds a first portion of the light-sensing region, and the first isolation structure has a first end portion in the substrate. The image sensor device includes a second isolation structure extending from the back surface into the substrate. The second isolation structure surrounds a second portion of the light-sensing region, the second isolation structure has a second end portion in the substrate, and the second end portion of the second isolation structure is closer to the front surface of the substrate than the first end portion of the first isolation structure.

Abstract: A display device includes: a substrate; a transistor positioned on the substrate; and a light-emitting device electrically connected to the transistor, wherein the substrate includes a first layer, a second layer positioned between the first layer and the transistor, and a third layer positioned between the second layer and the transistor, the first layer and the third layer include organic materials, and the organic material included by the first layer and the organic material included by the third layer have different half-lives for a corona discharge.

Abstract: An IC package structure including an array of package units formed into a panel-shaped package units array. Each package unit has a continuous and closed metal wall surrounding the periphery of the package unit and at least one IC chip/IC die disposed in the package unit, and wherein each IC chip/IC die has a top surface and a back surface opposite to the top surface. A panel-shaped metal layer corresponding to the panel-shaped package units array can be formed on entire back side of the IC package structure and bonded to the metal wall of each package unit, wherein the back side of the IC package structure refers to the side to which the back surface of each IC chip/IC die is facing.

Abstract: Discussed is a display device, including a substrate, a substrate electrode disposed on the substrate, a magnetic portion disposed and having a magnetic property on an upper surface of the substrate, and a plurality of light-emitting devices respectively disposed on the magnetic portion, wherein the each of the plurality of light-emitting devices includes a magnetic electrode forming an attractive force with the magnetic portion.

Abstract: A method of manufacturing the semiconductor structure includes: providing a substrate; forming a first conductive via and a second conductive via extending in the substrate; depositing a first dielectric layer over the substrate and the first and second conductive vias; receiving a waveguide; moving the waveguide to a location over the first dielectric layer and aligning the waveguide with a position of the first dielectric layer; attaching the waveguide to the position of the first dielectric layer; forming a first conductive member and a second conductive member over the waveguide, the first conductive member and the second conductive member being in contact with the waveguide; and etching a backside of the substrate to electrically expose the first and second conductive vias. The first conductive member or the second conductive member is electrically connected to the first or second conductive via.

Abstract: A system for controlling of wafer bow in plasma processing stations is described. The system includes a circuit that provides a low frequency RF signal and another circuit that provides a high frequency RF signal. The system includes an output circuit and the stations. The output circuit combines the low frequency RF signal and the high frequency RF signal to generate a plurality of combined RF signals for the stations. Amount of low frequency power delivered to one of the stations depends on wafer bow, such as non-flatness of a wafer. A bowed wafer decreases low frequency power delivered to the station in a multi-station chamber with a common RF source. A shunt inductor is coupled in parallel to each of the stations to increase an amount of current to the station with a bowed wafer. Hence, station power becomes less sensitive to wafer bow to minimize wafer bowing.

Abstract: A package component for carrying a device package and an insulating layer thereon includes a molding layer, first and second redistribution structures disposed on two opposite sides of the molding layer, a semiconductor die, and a through interlayer via (TIV). A hardness of the molding layer is greater than that of the insulating layer that covers the device package. The device package is mounted on the second redistribution structure, and the insulating layer is disposed on the second redistribution structure opposite to the molding layer. The semiconductor die is embedded in the molding layer and electrically coupled to the device package through the second redistribution structure. The TIV penetrates through the molding layer to connect the first and the second redistribution structure. An electronic device and a manufacturing method thereof are also provided.

Abstract: A LED structure includes a substrate, a plurality of LED units, a bonding layer and a metal contact. The substrate includes a driving circuit, and a plurality of LED units is formed on the substrate. The bonding layer is formed between the substrate and the plurality of LED units, and the metal contact is formed in the bonding layer beneath each LED unit to electrically connect each LED unit with a contact pad of the driving circuit. A first sectional area of the metal contact is smaller than a second sectional area of each LED unit.

Abstract: A method for fabricating a semiconductor device includes forming a through-hole penetrating through an alternating stack pattern and forming a gap-fill layer, wherein a sacrificial gap-fill layer of the gap-fill layer fills the through-hole. The method also includes forming a mask layer over the alternating stack pattern and over the gap-fill layer, wherein the mask layer includes a self-aligned opening overlapping the filled through-hole and overlapping a portion of an uppermost material layer of the alternating stack pattern adjacent to the filled through-hole. The method further includes forming a first contact hole through the alternating stack pattern by performing a single etch using both the mask layer and the portion of the uppermost material layer as etch barriers to remove, through the self-aligned opening, the sacrificial gap-fill layer filling the through-hole.

Abstract: A light emitting device may include: a substrate including a plurality of unit light emitting regions; and first to fourth insulating layers sequentially on the substrate.

Abstract: A microelectronic device has a die with a first electrically conductive pillar, and a second electrically conductive pillar, mechanically coupled to the die. The microelectronic device includes a first electrically conductive extended head electrically coupled to the first pillar, and a second electrically conductive extended head electrically coupled to the second pillar. The first pillar and the second pillar have equal compositions of electrically conductive material, as a result of being formed concurrently. Similarly, the first extended head and the second extended head have equal compositions of electrically conductive material, as a result of being formed concurrently. The first extended head provides a bump pad, and the second extended head provides at least a portion of a first plate of an integrated capacitor. A second plate may be located in the die, between the first plate and the die, or on an opposite of the first plate from the die.

Abstract: A display device includes a substrate, a first electrode and a second electrode which are spaced apart from each other on the substrate, a first insulating pattern on the substrate to cover at least a portion of each of the first electrode and the second electrode, a light emitting element between the first electrode and the second electrode on the first insulating pattern, a first contact electrode in contact with the first electrode and one end portion of the light emitting element, a second contact electrode in contact with the second electrode and another end portion of the light emitting element, and a second insulating pattern on the light emitting element and of which at least a portion is in contact with each of the first contact electrode and the second contact electrode, wherein the second insulating pattern includes a first upper surface not in contact with the first contact electrode or the second contact electrode.

Abstract: A semiconductor device includes a semiconductor device and a semiconductor fin on the semiconductor substrate, in which the semiconductor fin has a fin isolation structure at a common boundary that is shared by the two cells. The fin isolation structure has an air gap extending from a top of the semiconductor fin to a stop layer on the semiconductor substrate. The air gap divides the semiconductor fin into two portions of the semiconductor fin. The fin isolation structure includes a dielectric cap layer capping a top of the air gap.

Abstract: A light emitting device includes a first light emitting part including a first n-type semiconductor layer, and a first mesa structure including a first active layer, a first p-type semiconductor layer, and a first transparent electrode vertically stacked one over another and exposing a portion of a first surface of the first n-type semiconductor layer, a second light emitting part spaced apart from the first mesa structure, and including a second n-type semiconductor layer, a second active layer, a second p-type semiconductor layer, and a second transparent electrode and exposing a portion of a first surface of the second n-type semiconductor layer, and a first bonding layer on which the first and second light emitting parts are disposed and electrically coupling the first n-type semiconductor layer and the second n-type semiconductor layer to each other.

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a plurality of first dies on a substrate, an encapsulation layer over the first dies and the substrate, an interface layer over the first dies and the encapsulation layer, and a passive heat spreader on the interface layer, wherein the interface layer thermally couples the first dies to the passive heat spreader. The passive heat spreader includes a silicon (Si) or a silicon carbide (SiC). The interface layer includes a silicon nitride (SiN) material, a silicon monoxide (SiO) material, a silicon carbon nitride (SiCN) material, or a thermal adhesive material. The semiconductor package may include a plurality of second dies and the substrate on a package substrate, a thermal interface material (TIM) over the second dies, the passive heat spreader, and the package substrate, and a heat spreader over the TIM and the package substrate.