Patents Examined by Victor A. Mandala
  • Patent number: 11876149
    Abstract: Provided is a display device including a substrate, a transfer guiding mold provided on the substrate and including a plurality of openings, and a plurality of micro light emitting diodes (LEDs) provided on the substrate in the plurality of openings, wherein a height of the transfer guiding mold is less than twice a height of each of the plurality of micro LEDs.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: January 16, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyungwook Hwang, Sungjin Kang, Junsik Hwang, Junhee Choi
  • Patent number: 11876075
    Abstract: The present application discloses a semiconductor device. The semiconductor device includes a package structure including a first side and a second side opposite to the first side; an interposer structure positioned over the first side of the package structure; a first die positioned over the interposer structure; a second die positioned over the interposer structure; and a plurality of bottom interconnectors positioned on the second side of the package structure, and respectively including: a bottom exterior layer positioned on the second side of the package structure; a bottom interior layer enclosed by the bottom exterior layer; and a cavity enclosed by the bottom interior layer.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: January 16, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chun-Heng Wu
  • Patent number: 11870022
    Abstract: A package includes a substrate, a first light-emitting unit, a second light-emitting unit, a light-transmitting layer, and a light-absorbing layer. The substrate has a first surface and an upper conductive layer on the first surface. The first light-emitting unit and the second light-emitting unit are disposed on the upper conductive layer. The first light-emitting unit has a first light-emitting surface and a first side wall. The second light-emitting unit has a second light-emitting surface and a second side wall. The light-transmitting layer is disposed on the first surface and covers the upper conductive layer, the first light-emitting unit, and the second light-emitting unit. The light-absorbing layer is disposed between the substrate and the light-transmitting layer, covers the upper conductive layer, the first side wall, and the second side wall, and exposes the first light-emitting surface and the second light-emitting surface.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: January 9, 2024
    Assignees: EPISTAR CORPORATION, YENRICH TECHNOLOGY CORPORATION
    Inventors: Shau-Yi Chen, Tzu-Yuan Lin, Wei-Chiang Hu, Pei-Hsuan Lan, Min-Hsun Hsieh
  • Patent number: 11870025
    Abstract: A display device includes a first substrate, a wire pad in a pad area, first banks in a display area, electrodes on the first banks, a pad electrode base layer on the wire pad, having a greater width than the wire pad, and covering sides of the wire pad, a first insulating layer covering parts of the electrodes and part of the pad electrode base layer, light-emitting elements on the first insulating layer in the display area, respective ends of the light-emitting elements being on different electrodes, contact electrodes on the electrodes and contacting first ends of the light-emitting elements, and a pad electrode upper layer on the first insulating layer in the pad area and directly contacting the pad electrode base layer, wherein the pad electrode base layer includes the same material as the electrodes, and the pad electrode upper layer includes the same material as the contact electrodes.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: January 9, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jin Taek Kim, Seung Min Lee, Jung Hwan Yi, Hee Keun Lee, Bek Hyun Lim, Kyung Tae Chae
  • Patent number: 11869816
    Abstract: A package substrate comprises first, second and third electrical test contacts, wherein the package substrate is provided with an upper element plane and a lower SMD electrode plane on two sides. The side edge of the upper element plane is provided with first and second electrodes of the main element and first and second electrodes of the secondary element. The main element of LED chip is electrically connected between the first and second electrodes of the main element, a parallel circuit secondary element is electrically connected between the first and second electrodes of the secondary element. The electrical characteristics of the main element of LED chip and the parallel circuit secondary element are measured through the first, second, and third electrical test contacts when electrically connected.
    Type: Grant
    Filed: July 26, 2021
    Date of Patent: January 9, 2024
    Assignee: EXCELLENCE OPTO. INC.
    Inventors: Fu-Bang Chen, Chih-Chiang Chang, Chang-Ching Huang, Chun-Ming Lai, Wen-Hsing Huang, Tzeng-Guang Tsai, Kuo-Hsin Huang
  • Patent number: 11869772
    Abstract: A exemplary semiconductor device includes a first gate structure overlying a surface of the semiconductor body, the first gate structure being silicided. A second gate structure overlies the surface of the semiconductor body and not being silicided. An oxide layer overlies the second gate structure and extends toward the first gate structure. A silicon nitride region is laterally spaced from the second gate structure and overlies a portion of the oxide layer between the first gate structure and the second gate structure.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: January 9, 2024
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Denis Monnier, Olivier Gonnard
  • Patent number: 11862539
    Abstract: A packaged electronic device includes a substrate having a lead. The lead includes an outward facing side surface having a first height, and an inward facing side surface having a second height that is less than the first height. An electronic device is electrically connected to the lead. A package body encapsulates the electronic device and portions of the lead. The outward facing side surface is exposed through a side surface of the package body, and the inward facing side surface is encapsulated by the package body. A conductive layer is disposed on the outward facing side surface to provide the packaged electronic device with an enhanced wettable flank. In one embodiment, the electronic device is electrically connected to a thick terminal portion having the outward facing side surface. In another embodiment, the electronic device is electrically connected to a thin terminal portion having the inward facing side surface.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: January 2, 2024
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventor: Pedro Joel Rivera-Marty
  • Patent number: 11862685
    Abstract: The wafer having a retardation distribution measured with a light having a wavelength of 520 nm, wherein an average value of the retardation is 38 nm or less, wherein the wafer comprises a micropipe, and wherein a density of the micropipe is 1.5/cm2 or less, is disclosed.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: January 2, 2024
    Assignee: SENIC INC.
    Inventors: Jong Hwi Park, Kap-Ryeol Ku, Jung-Gyu Kim, Jung Woo Choi, Myung-Ok Kyun
  • Patent number: 11864386
    Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. The individual memory cells comprise a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode electrically couples to the first source/drain region. Wordline structures extend elevationally through the insulative material and the memory cells of the vertically-alternating tiers. Individual of the gates that are in different of the memory cell tiers directly electrically couple to individual of the wordline structures. Sense-lines electrically couple to multiple of the second source/drain regions of individual of the transistors. Other embodiments are disclosed.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: January 2, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Sanh D. Tang, Richard J. Hill, Yi Fang Lee, Martin C. Roberts
  • Patent number: 11862710
    Abstract: A semiconductor device includes a first source/drain region on an upper surface of a semiconductor substrate that extends along a first direction to define a length and a second direction opposite the first direction to define a width. A channel region extends vertically in a direction perpendicular to the first and second directions from a first end contacting the first source/drain region to an opposing second end contacting a second source/drain region. A gate surrounds a channel portion of the channel region, and a first doped source/drain extension region is located between the first source/drain region and the channel portion. The first doped source/drain extension region has a thickness extending along the vertical direction. A second doped source/drain extension region is located between the second source/drain region and the channel portion. The second doped source/drain extension region has a thickness extending along the vertical direction that matches the first thickness.
    Type: Grant
    Filed: January 6, 2022
    Date of Patent: January 2, 2024
    Assignee: International Business Machines Corporation
    Inventors: Chun-Chen Yeh, Alexander Reznicek, Veeraraghavan Basker, Junli Wang
  • Patent number: 11856795
    Abstract: Present disclosure provides a semiconductor structure and a method for fabricating a semiconductor device. The semiconductor includes a transistor, a first metallization layer over the transistor, a phase change material over the first metallization layer, a second metallization layer over the phase change material, a heater between the first metallization layer and the second metallization layer and in contact with the phase change material, the heater including a heat insulation shell having a first heat conductivity, wherein the heat insulation shell includes a superlattice structure, and a heat conducting core contacting the heat insulation shell and having a second heat conductivity different from the first heat conductivity.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventor: Jau-Yi Wu
  • Patent number: 11849637
    Abstract: The present disclosure provides a nitrogen-containing compound, an electronic component comprising same, and an electronic device, and belongs to the technical field of organic electroluminescence. In the compound of the present disclosure, the nitrogen-containing compound is more suitable for being used as an electronic-type host material in the mixed host of the luminescence layer of an organic electroluminescent device, and is especially suitable for being used as an electronic-type host material in a green light device. When the nitrogen-containing compound of the present disclosure is used as a luminescence layer material of the organic electroluminescent device, the electron transporting performance of the device is effectively improved, the luminescence efficiency of the device is improved, and the service life of the device is prolonged.
    Type: Grant
    Filed: August 10, 2021
    Date of Patent: December 19, 2023
    Assignee: Shaanxi Lighte Optoelectronics Material Co., Ltd.
    Inventors: Tiantian Ma, Yan Zang, Peng Nan
  • Patent number: 11842987
    Abstract: A display panel including a circuit board having pads, light emitting devices electrically connected to the pads and arranged on the circuit board, each light emitting device having a first surface facing the circuit board and a second surface opposite to the first surface, a buffer material layer disposed between the circuit board and the light emitting devices to fill a space between the circuit board and the light emitting devices, and a cover layer covering the second surface of the light emitting devices, in which the buffer material layer is disposed under the first surfaces of the light emitting devices and has grooves in a region between adjacent light emitting devices, a portion of a top surface of the buffer material layer is disposed between adjacent light emitting devices, and the cover layer fills the grooves of the buffer material layer.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: December 12, 2023
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Seong Kyu Jang, Seom Geun Lee, Chan Seob Shin, Ho Joon Lee
  • Patent number: 11837584
    Abstract: A manufacturing method of a display device is provided. The manufacturing method of the display device includes forming a switching structure. The switching structure includes a plurality of switching elements. The manufacturing method of the display device also includes forming a light-emitting structure. The light-emitting structure includes a plurality of light-emitting elements. The manufacturing method of the display device further includes arranging the light-emitting structure on the switching structure, so that each of the light-emitting elements is above each of the switching elements. The manufacturing method of the display device includes connecting each of the light-emitting elements to a corresponding switching element via a laser.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: December 5, 2023
    Assignee: ACER INCORPORATED
    Inventors: Jui-Chieh Hsiang, Chih-Chiang Chen
  • Patent number: 11837593
    Abstract: A method and structure for receiving a micro device on a receiving substrate are disclosed. A micro device such as a micro LED device is punched-through a passivation layer covering a conductive layer on the receiving substrate, and the passivation layer is hardened. In an embodiment the micro LED device is punched-through a B-staged thermoset material. In an embodiment the micro LED device is punched-through a thermoplastic material.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: December 5, 2023
    Assignee: Apple Inc.
    Inventors: John A Higginson, Andreas Bibl, Hsin-Hua Hu
  • Patent number: 11837662
    Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device of the present disclosure includes a first fin including a first source/drain region, a second fin including a second source/drain region, a first isolation layer disposed between the first source/drain region and the second source/drain region, and a second isolation layer disposed over the first isolation layer. A first portion of the first isolation layer is disposed on sidewalls of the first source/drain region and a second portion of the first isolation layer is disposed on sidewalls of the second source/drain region. A portion of the second isolation layer is disposed between the first portion and second portion of the first isolation layer.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: December 5, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Xusheng Wu, Chang-Miao Liu, Huiling Shang
  • Patent number: 11837591
    Abstract: A manufacturing method of a light emitting diode (LED) package structure includes the following steps. A carrier is provided. A redistribution layer is formed on the carrier. A plurality of active devices are formed on the carrier. A plurality of LEDs are transferred on the redistribution layer. The LEDs and the active devices are respectively electrically connected to the redistribution layer. The active devices are adapted to drive the LEDs, respectively. A molding compound is formed on the redistribution layer to encapsulate the LEDs. The carrier is removed to expose a bottom surface of the redistribution layer.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: December 5, 2023
    Assignee: Unimicron Technology Corp.
    Inventors: Ming-Ru Chen, Tzyy-Jang Tseng, Cheng-Chung Lo
  • Patent number: 11837625
    Abstract: A display apparatus including a display substrate, light emitting devices disposed on the display substrate, circuit electrodes disposed between the light emitting devices and the display substrate, and a transparent layer covering the light emitting devices and the circuit electrodes, in which at least one of the light emitting devices includes a first LED sub-unit configured to emit light having a first wavelength, a second LED sub-unit adjacent to the first LED sub-unit and configured to emit light having a second wavelength, a third LED sub-unit adjacent to the second LED sub-unit and configured to emit light having a third wavelength, and a substrate disposed on the third LED sub-unit, in which a difference in refractive indices between the transparent layer and air is less than a difference in refractive indices between the substrate and a semiconductor layer of the third LED sub-unit.
    Type: Grant
    Filed: October 30, 2022
    Date of Patent: December 5, 2023
    Assignee: Seoul Viosys Co., Ltd.
    Inventors: Chung Hoon Lee, Dae Sung Cho
  • Patent number: 11837537
    Abstract: A fan-out semiconductor package includes a first connection structure having first and second surfaces, a first semiconductor chip disposed on the first surface, a first encapsulant disposed on the first surface and covering at least a portion of the first semiconductor chip, a second semiconductor chip disposed on the second surface, one or more first metal members disposed on the second surface, one or more second metal members disposed on the second surface, a second encapsulant disposed on the second surface and respectively covering at least portions of the second semiconductor chip and the first and second metal members, and a second connection structure disposed on an opposite side of a side of the second encapsulant, on which the first connection structure is disposed.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: December 5, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bongju Cho, Myungsam Kang, Younggwan Ko, Gun Lee, Jaekul Lee
  • Patent number: 11830782
    Abstract: In a semiconductor device, it is preferable to suppress a variation in characteristics of a temperature sensor. The semiconductor device is provided that includes a semiconductor substrate having a first conductivity type drift region, a transistor section provided in the semiconductor substrate, a diode section provided in the semiconductor substrate, a second conductivity type well region exposed at an upper surface of the semiconductor substrate, a temperature sensing unit that is adjacent to the diode section in top view and is provided above the well region, and an upper lifetime control region that is provided in the diode section, at the upper surface side of the semiconductor substrate, and in a region not overlapping with the temperature sensing unit in top view.
    Type: Grant
    Filed: May 11, 2021
    Date of Patent: November 28, 2023
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Motoyoshi Kubouchi, Soichi Yoshida