Abstract: An aggregate die comprises a substrate, a first sub die, and a second sub die. The substrate comprises a surface with a first set of substrate alignment guides and a second set of substrate alignment guides. The first sub die comprises a first set of sub die alignment guides that interface with the substrate alignment guides in the first set of substrate alignment guides. The second sub die comprises a second set of sub die alignment guides that interface with substrate alignment guides in the second set of substrate alignment guides.

Abstract: Representative implementations provide techniques for processing integrated circuit (IC) dies and related devices, in preparation for stacking and bonding the devices. The disclosed techniques provide removal of processing residue from the device surfaces while protecting the underlying layers. One or more sacrificial layers may be applied to a surface of the device during processing to protect the underlying layers. Processing residue is attached to the sacrificial layers instead of the device, and can be removed with the sacrificial layers.

Abstract: A Metal Oxide Semiconductor (MOS) cell design has traditional planar cells extending in a first dimension, and trenches with their length extending in a third dimension, orthogonal to the first dimension in a top view. The manufacturing process includes forming a horizontal channel, and a plurality of trenches discontinued in the planar cell regions. Horizontal planar channels are formed in the mesa of the orthogonal trenches. A series connected horizontal planar channel and a vertical trench channel are formed along the trench regions surrounded by the first base. The lack of a traditional vertical channel is important to avoid significant reliability issues (shifts in threshold voltage Vth). The planar cell design offers a range of advantages both in terms of performance and processability. Manufacture of the planar cell is based on a self-aligned process with minimum number of masks, with the potential of applying additional layers or structures.

Abstract: A stacked transistor structure including a top source drain region above a bottom source drain region, wherein a width of the bottom source drain region is greater than a width of the top source drain region, a bottom contact structure directly above and in electrical contact with the bottom source drain region, a replacement spacer surrounding the bottom contact structure, and a top gate spacer separating the replacement spacer from a gate conductor.

Abstract: The present application discloses a super junction device, which includes: an N-type redundant epitaxial layer and an N-type buffer layer sequentially formed on an N-type semiconductor substrate; a trench filled super junction structure is formed on the N-type buffer layer; a back structure includes a drain region and a patterned back P-type impurity region; the N-type semiconductor substrate is removed in a back thinning process, and the N-type redundant epitaxial layer is completely or partially removed in the back thinning process; the resistivity of the N-type semiconductor substrate is 0.1-10 times the resistivity of a top epitaxial layer, the resistivity of the N-type redundant epitaxial layer is 0.1-10 times the resistivity of the N-type semiconductor substrate, and the resistivity of the N-type redundant epitaxial layer is lower than the resistivity of the N-type buffer layer. The present application further discloses a method for manufacturing a super junction device.

Abstract: A display device is provided. In per unit area of the display device, a light-concentrating intensity of light emitted from sub-pixels in a non-planar display area and passing through a first optical film layer and a second optical film layer at a front viewing angle is less than a light-concentrating intensity of light emitted from the sub-pixels in a planar display area and passing through the first optical film layer and the second optical film layer at the front viewing angle. Poor user experiences at a certain viewing angle in the non-planar display area can be improved.

Abstract: A display device may include: a base layer including a display area and a non-display area; and a plurality of pixels provided on the display area, and each including a plurality of sub-pixels. Each of the sub-pixels may include a pixel circuit layer, and a display element layer including an emission area formed to emit light, and a non-emission area provided around a perimeter of the emission area. The display element layer may include: a partition wall provided on the emission area of each of the sub-pixels; a bank provided on the non-emission area of each sub-pixel, and disposed on a surface equal to a surface on which the partition wall is disposed; a first electrode and a second electrode provided on the partition wall and spaced apart from each other; and at least one light emitting element provided between the first and second electrodes in the emission area of each sub-pixel, and configured to emit the light.

Abstract: Provided is an imaging element including a photoelectric conversion unit formed by stacking a first electrode, a photoelectric conversion layer and a second electrode. The photoelectric conversion unit further includes a charge storage electrode which is disposed to be spaced apart from the first electrode and disposed opposite to the photoelectric conversion layer via an insulating layer. The photoelectric conversion unit is formed of N number of photoelectric conversion unit segments, and the same applies to the photoelectric conversion layer, the insulating layer and the charge storage electrode. An nth photoelectric conversion unit segment is formed of an nth charge storage electrode segment, an nth insulating layer segment and an nth photoelectric conversion layer segment. As n increases, the nth photoelectric conversion unit segment is located farther from the first electrode. A thickness of the insulating layer segment gradually changes from a first to Nth photoelectric conversion unit segment.

Abstract: A semiconductor device includes a nucleation layer, a buffer layer, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, S/D electrodes, and a gate electrode. The nucleation layer includes a composition that includes a first element. The buffer layer includes a III-V compound which includes the first element. The buffer layer is disposed on and forms an interface with the nucleation layer. The buffer layer has a concentration of the first element oscillating within the buffer layer, such that the concentration of the first element varies as an oscillating function of a distance within a thickness of the buffer layer. An oscillation rate in the concentration of the first element per unit thickness of the buffer layer varies with respect to a first reference point within the buffer layer. The first and second nitride-based semiconductor layer, S/D electrodes, and a gate electrode are disposed on the buffer layer.

Abstract: A semiconductor device includes a nucleation layer, a buffer layer, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, S/D electrodes, and a gate electrode. The nucleation layer includes a composition that includes a first element. The buffer layer includes a III-V compound which includes the first element. The buffer layer has a concentration of the first element oscillating within the buffer layer, such that the concentration of the first element varies as an oscillating function of a distance within a thickness of the buffer layer. A first oscillation rate between a first reference point and a second reference point within the buffer layer is less than a second oscillation rate between the second reference point and a third reference point within the buffer layer. The first and second nitride-based semiconductor layer, S/D electrodes, and a gate electrode are disposed on the buffer layer.

Abstract: A semiconductor device includes a nucleation layer, a buffer layer, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, S/D electrodes, and a gate electrode. The nucleation layer includes a composition that includes a first element. The buffer layer includes a III-V compound which includes the first element. The buffer layer has a concentration of the first element oscillating within the buffer layer, such that the concentration of the first element varies as an oscillating function of a distance within a thickness of the buffer layer. A first oscillation rate between a first reference point and a second reference point within the buffer layer is greater than a second oscillation rate between the second reference point and a third reference point within the buffer layer. The first and second nitride-based semiconductor layer, S/D electrodes, and a gate electrode are disposed on the buffer layer.

Abstract: An optical module of the present disclosure includes a first panel including a first light-emitting element, a first power supply wiring and a second power supply wiring; a second panel including a second light-emitting element having light emission luminance per unit current lower than that of the first light-emitting element, a third power supply wiring and a fourth power supply wiring; and a prism configured to synthesize first image light emitted from the first panel and second image light emitted from the second panel. A first potential difference is smaller than a second potential difference, the first potential difference being a difference between a potential applied to the first power supply wiring and a potential applied to the second power supply wiring, the second potential difference being a difference between a potential applied to the third power supply wiring and a potential applied to the fourth power supply wiring.

Abstract: A semiconductor device includes a nucleation layer, a buffer layer, a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, S/D electrodes, and a gate electrode. The nucleation layer includes a composition that includes a first element. The buffer layer includes a III-V compound which includes the first element. The buffer layer is disposed on and forms an interface with the nucleation layer. The buffer layer has a concentration of the first element oscillating within the buffer layer, such that the concentration of the first element varies as an oscillating function of a distance within a thickness of the buffer layer. Spacings among adjacent peaks of the oscillating function change from narrow to wide with respect to a first reference point within the buffer layer. The first and second nitride-based semiconductor layer, S/D electrodes, and a gate electrode are disposed on the buffer layer.

Abstract: A capacitor structure and a method of manufacturing the same, and a memory are provided. The method includes the following operations. A substrate is provided. A first conductive structure with a shape of column is formed on the substrate. A second conductive structure is formed on the substrate. The second conductive structure surrounds the first conductive structure and is spaced with the first conductive structure. The first conductive structure and the second conductive structure together form a bottom electrode. A capacitor dielectric layer is formed. The capacitor dielectric layer covers the surface of the substrate and the surface of the bottom electrode. A top electrode covering the surface of the capacitor dielectric layer is formed.

Abstract: Semiconductor devices, and in particular protection structures for semiconductor devices that include sensor arrangements are disclosed. A semiconductor device may include a sensor region, for example a current sensor region that occupies a portion of an overall active area of the device. The current sensor region may be configured to provide monitoring of device load currents during operation. Semiconductor devices according to the present disclosure include one or more protection structures that are configured to allow the semiconductor devices to withstand transient voltage events without device failure. A protection structure may include an insulating layer that is provided in a transition region between a device region and the sensor region of the semiconductor device. In the example of an insulated gate semiconductor device, the insulating layer of the protection structure may include a material with a greater breakdown voltage than a breakdown voltage of a gate insulating layer.

Abstract: According to one embodiment, a semiconductor device includes a circuit pattern including a plurality of unit patterns that are disposed in a repeating manner in at least one direction. The semiconductor device includes a discrimination pattern provided in the circuit pattern and configured to discriminate the unit patterns from each other.

Abstract: The present disclosure relates to a semiconductor mark and a forming method thereof. The semiconductor mark comprises: a previous layer mark comprising first patterns and at least one second pattern, the second pattern being located between adjacent first patterns, the first pattern being different from the second pattern in material property. Since the first pattern and the second pattern in the previous layer mark in the semiconductor mark according to the present disclosure are different in material property, during measurement, the first pattern and the second pattern are different in reflectivity for measurement light. Thus, the contrast of images of the first pattern and the second pattern obtained during measurement is improved, the positions and boundaries of the first pattern and the second pattern are clearly determined, and the measurement of the previous layer mark is more accurate.

Abstract: An optoelectronic component includes an optical transducer made of III-V semiconductor material and an optical scanning microelectromechanical system comprising a mirror. The optical transducer and the optical scanning microelectromechanical system are produced on a common wafer comprising at least a first layer made of silicon or silicon nitride with a thickness of less than one micron and wherein at least the mirror and its holding springs are produced. In a first variant, the mobile parts of the optical scanning microelectromechanical system are produced in various layers of silicon. In a second variant, the mobile parts of the optical scanning microelectromechanical system are produced in the layer of III-V semiconductor material.

Abstract: An open through-substrate via, TSV, comprises an insulation layer disposed adjacent to at least a portion of side walls of a trench and to a surface of a substrate body. The TSV further comprises a metallization layer disposed adjacent to at least a portion of the insulation layer and to at least a portion of a bottom wall of said trench, a redistribution layer disposed adjacent to at least a portion of the metallization layer and a portion of the insulation layer disposed adjacent to the surface, and a capping layer disposed adjacent to at least a portion of the metallization layer and to at least a portion of the redistribution layer. The insulation layer and/or the capping layer comprise sublayers that are distinct from each other in terms of material properties. A first of the sublayers is disposed adjacent to at least a portion of the side walls and to at least a portion of the surface and a second of the sublayers is disposed adjacent to at least a portion of the surface.

Abstract: Solid-state transducer (“SST”) dies and SST arrays having electrical cross-connections are disclosed herein. An array of SST dies in accordance with a particular embodiment can include a first terminal, a second terminal and a plurality of SST dies coupled between the first and second terminals with at least a pair of the SST dies being coupled in parallel. The plurality of SST dies can individually include a plurality of junctions coupled in series with an interconnection between each individual junction. Additionally, the individual SST dies can have a cross-connection contact coupled to the interconnection. In one embodiment, the array can further include a cross-connection between the cross-connection contacts on the pair of the SST dies.