Patents Examined by Victor V Barzykin
  • Patent number: 11489042
    Abstract: A semiconductor device is provided.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: November 1, 2022
    Inventors: Jaegil Lee, Sangtae Han
  • Patent number: 11486562
    Abstract: Systems for apparatuses formed of light emitting devices. Solutions for controlling the off-state appearance of lighting system designs is disclosed. Thermochromic materials are selected in accordance with a desired off-state of an LED device. The thermochromic materials are applied to a structure that is in a light path of light emitted by the LED device. In the off-state the LED device produces a desired off-state colored appearance. When the LED device is in the on-state, the thermochromic materials heat up and become more and more transparent. The light emitted from the device in its on-state does not suffer from color shifting due to the presence of the thermochromic materials. Furthermore, light emitted from the LED device in its on-state does not suffer from attenuation due to the presence of the thermochromic materials. Techniques to select and position thermochromic materials in or around LED apparatuses are presented.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: November 1, 2022
    Assignee: Lumileds LLC
    Inventors: Hisashi Masui, Oleg Shchekin, Ken Shimizu, Marcel Bohmer, Frank Jin, Jyoti Bhardwaj
  • Patent number: 11450564
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a gate structure on a substrate; forming a source/drain region adjacent to two sides of the gate structure; forming an interlayer dielectric (ILD) layer on the gate structure; forming a contact hole in the ILD layer to expose the source/drain region; forming a barrier layer in the contact hole; performing an anneal process; and performing a plasma treatment process to inject nitrogen into the contact hole.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: September 20, 2022
    Inventors: Jin-Yan Chiou, Wei-Chuan Tsai, Yen-Tsai Yi, Li-Han Chen, Hsiang-Wen Ke
  • Patent number: 11444088
    Abstract: Some embodiments include a method of forming an integrated assembly. A structure is provided to have conductive lines, and to have rails over the conductive lines and extending in a direction which crosses the conductive lines. Each of the rails includes pillars of semiconductor material. The rails have sidewall surfaces along spaces between the rails. The pillars have upper segments, middle segments and lower segments. First-material liners are formed along the sidewall surfaces of the rails. A second material is formed over the liners. First sections of the liners are removed to form gaps between the second material and the sidewall surfaces of the rails. Second sections of the liners remain under the gaps. Conductive material is formed within the gaps. The conductive material is configured as conductive lines which are along the middle segments of the pillars.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: September 13, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Hong Li, Ramaswamy Ishwar Venkatanarayanan, Sanh D. Tang, Erica L. Poelstra
  • Patent number: 11417811
    Abstract: A light emitting element includes a semiconductor stacked body, an insulating film, first and second electrodes, a second external connection portion, and first external connection portions. The first semiconductor layer is exposed at a plurality of exposed portions disposed in a plurality of rows in plan view. The first external connection portions include at least one smaller-size first external connection portion disposed between adjacent ones of the rows other than the outermost one of the rows, and at least one larger-size first external connection portion extending from the end region, in which a spacing between a first outer edge of a second semiconductor layer and the exposed portions in the outermost one of the rows is narrower than a spacing between the exposed portions in adjacent ones of the rows, to at least a position between the outermost one of the rows and an adjacent one of the rows.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: August 16, 2022
    Inventors: Koichi Takenaga, Takanori Fukumori, Satoshi Shichijo, Hiroki Fukuta, Kunihito Sugimoto
  • Patent number: 11410990
    Abstract: A silicon carbide MOSFET device includes a gate pad area, a main MOSFET area and a secondary MOSFET area. A main source contact is electrically coupled to the source region of each of the main MOSFETs, and a separate secondary source contact is electrically coupled to the source region of each of the secondary MOSFETs. A gate contact electrically connects to each of the insulated gate members of the main and secondary MOSFETs. An asymmetric gate clamping circuit is coupled between the secondary source contact and the gate contact. In a first mode of operation of the MOSFET device the main source contact is electrically coupled with the secondary source contact to activate the gate clamping circuit. When activated, the circuit clamping a gate-to-source voltage to a first clamp voltage in an on-state of the MOSFET device, and to a second clamp voltage in an off-state of the MOSFET device.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: August 9, 2022
    Inventors: Rahul R. Potera, Carl A. Witt
  • Patent number: 11404457
    Abstract: An image sensor may include a substrate including a plurality of unit pixel regions and having first and second surfaces facing each other. Each of the unit pixel regions may include a plurality of floating diffusion parts spaced apart from each other in the substrate, storage nodes provided in the substrate to be spaced apart from and facing the floating diffusion parts, a transfer gate adjacent to a region between the floating diffusion parts and the storage nodes, and photoelectric conversion parts sequentially stacked on one of the first and second surfaces. Each of the photoelectric conversion parts may include common and pixel electrodes respectively provided on top and bottom surfaces thereof and each pixel electrode may be electrically connected to a corresponding one of the storage nodes.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: August 2, 2022
    Inventors: Gwi-Deok Ryan Lee, Taeyon Lee
  • Patent number: 11404309
    Abstract: Interconnect structures and corresponding techniques for forming the interconnect structures are disclosed herein. An exemplary interconnect structure includes a conductive feature that includes cobalt and a via disposed over the conductive feature. The via includes a first via barrier layer disposed over the conductive feature, a second via barrier layer disposed over the first via barrier layer, and a via bulk layer disposed over the second via barrier layer. The first via barrier layer includes titanium, and the second via barrier layer includes titanium and nitrogen. The via bulk layer can include tungsten and/or cobalt. A capping layer may be disposed over the conductive feature, where the via extends through the capping layer to contact the conductive feature. In some implementations, the capping layer includes cobalt and silicon.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: August 2, 2022
    Inventors: Yu-Jen Chang, Min-Yann Hsieh, Hua Feng Chen, Kuo-Hua Pan
  • Patent number: 11404535
    Abstract: A method includes forming a layer stack with a plurality of first layers of a first doping type and a plurality of second layers of a second doping type complementary to the first doping type on top of a carrier. Forming the layer stack includes forming a plurality of epitaxial layers on the carrier. Forming each of the plurality of epitaxial layers includes depositing a layer of semiconductor material, forming at least two first implantation regions of one of a first type or a second type at different vertical positions of the respective layer of semiconductor material, and forming at least one second implantation region of a type that is complementary to the type of the first implantation regions, the first implantation regions and the second implantation regions being arranged alternatingly.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: August 2, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Rolf Weis, Richard Hensch, Ahmed Mahmoud
  • Patent number: 11393800
    Abstract: A display device and a manufacturing method of a display device are provided. The display device includes a substrate, a plurality of first light-emitting elements, and at least one second light-emitting element. The first light-emitting elements are arranged on the substrate. A plurality of first electrodes are provided on a surface of each of the first light-emitting elements facing away from the substrate. The second light-emitting element is disposed on the substrate. A plurality of second electrodes are provided on a surface of the second light-emitting element facing away from the substrate. An orthographic projection of the second light-emitting element on the substrate partially overlaps orthographic projections of the first light-emitting elements on the substrate.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: July 19, 2022
    Assignee: Au Optronics Corporation
    Inventors: Yi-Fen Lan, Tsung-Tien Wu
  • Patent number: 11393779
    Abstract: Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: July 19, 2022
    Inventors: Guilian Gao, Bongsub Lee, Gaius Gillman Fountain, Jr., Cyprian Emeka Uzoh, Laura Wills Mirkarimi, Belgacem Haba, Rajesh Katkar
  • Patent number: 11387264
    Abstract: A substrate includes a photoelectric converting unit in a pixel unit and a reflection ratio adjusting layer provided on the substrate in an incident direction of incident light with respect to the substrate for adjusting reflection of the incident light on the substrate. The reflection ratio adjusting layer includes a first layer formed on the substrate and a second layer formed on the first layer, the first layer has an uneven structure provided on the substrate, and a recess portion on the uneven structure is filled with a material having a lower refractive index than that of the substrate forming the second layer, and a thickness of the first layer is optimized for a wavelength of light to be received. The present technology may be applied to an imaging device.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: July 12, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Koichi Takeuchi
  • Patent number: 11385552
    Abstract: An overlay metrology target (T) is formed by a lithographic process. A first image (740(0)) of the target structure is obtained using with illuminating radiation having a first angular distribution, the first image being formed using radiation diffracted in a first direction (X) and radiation diffracted in a second direction (Y). A second image (740(R)) of the target structure using illuminating radiation having a second angular illumination distribution which the same as the first angular distribution, but rotated 90 degrees. The first image and the second image can be used together so as to discriminate between radiation diffracted in the first direction and radiation diffracted in the second direction by the same part of the target structure. This discrimination allows overlay and other asymmetry-related properties to be measured independently in X and Y, even in the presence of two-dimensional structures within the same part of the target structure.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: July 12, 2022
    Assignee: ASML Netherlands B.V.
    Inventors: Martin Jacobus Johan Jak, Kaustuve Bhattacharyya
  • Patent number: 11387326
    Abstract: A silicon carbide semiconductor device includes: a silicon carbide semiconductor substrate that has a front surface and a rear surface; and a plurality of ohmic electrodes that are in ohmic contact with a surface of silicon carbide on at least one of the front surface and the rear surface of the silicon carbide semiconductor substrate. The plurality of ohmic electrodes are scattered on the surface of the silicon carbide to provide a concavity and convexity. The concavity and convexity has a height due to the ohmic electrodes less than 1.0 ?m.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: July 12, 2022
    Inventors: Kentarou Okumura, Hidekazu Odake, Hajime Tsukahara, Yukihiko Watanabe
  • Patent number: 11355543
    Abstract: A packaging unit, a component packaging structure and a preparation method thereof. The packaging unit includes a bonding substrate and spacers formed on the bonding substrate through a patterning process, wherein the bonding substrate is reserved with packaging regions for applying sealant. When the packaging unit is used to package a component, because the spacer(s) is supported between the bonding substrate and the base substrate, the packaging unit is easy to separate from the base substrate At the same time, the packaging unit has little or no damage to the base substrate and elements formed on the base substrate, thus effectively protecting the performance of the base substrate and the elements on the base substrate.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: June 7, 2022
    Inventors: Tingze Dong, Yan Yang, Hailong Zhou, Xian Li, Limin Tian
  • Patent number: 11355446
    Abstract: The present disclosure relates to a semiconductor chip scale package including a semiconductor die. The semiconductor die has a first major surface opposing a second major surface, a plurality of side walls extending between the first major surface and second major surface, a plurality of electrical contacts arranged on the second major surface of the semiconductor die, and an insulating material disposed on the plurality of side walls and on the first major surface. The insulating material includes a machine readable identifier by which a semiconductor chip scale packaging type is identifiable by an identification apparatus that reads the machine readable identifier, and the machine readable identifier includes a colour component.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: June 7, 2022
    Assignee: Nexperia B.V.
    Inventors: Tobias Sprogies, Jan Fischer
  • Patent number: 11348801
    Abstract: Representative implementations provide techniques for processing integrated circuit (IC) dies and related devices, in preparation for stacking and bonding the devices. The disclosed techniques provide removal of processing residue from the device surfaces while protecting the underlying layers. One or more sacrificial layers may be applied to a surface of the device during processing to protect the underlying layers. Processing residue is attached to the sacrificial layers instead of the device, and can be removed with the sacrificial layers.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: May 31, 2022
    Inventors: Cyprian Emeka Uzoh, Guilian Gao
  • Patent number: 11329002
    Abstract: Fabrication of an alignment mark in a semiconductor device is simplified. A semiconductor device including a semiconductor substrate, an epitaxial layer, and an alignment mark is provided. The epitaxial layer included in the semiconductor device includes a single-crystalline semiconductor that is epitaxially grown on a surface of the semiconductor substrate included in the semiconductor device. The alignment mark included in the semiconductor device is disposed between the semiconductor substrate and the epitaxial layer.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: May 10, 2022
    Inventors: Teruyuki Sato, Shinichi Arakawa, Takayuki Enomoto, Yohei Chiba
  • Patent number: 11322532
    Abstract: The backside illuminated image sensor comprises a substrate of semiconductor material, detector elements arranged at a main surface, a dielectric layer on or above the main surface, a first capacitor layer and a second capacitor layer above the main surface, the capacitor layers forming a capacitor (C1, C2). A peripheral circuit is integrated in the substrate apart from the detector elements, the peripheral circuit being configured for one or more operations of the group consisting of voltage regulation, charge pump operation and stabilization of clock generation, and the capacitor layers are electrically connected with contact regions of the peripheral circuit.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: May 3, 2022
    Assignee: AMSAG
    Inventor: Guy Meynants
  • Patent number: 11316036
    Abstract: An insulated gate bipolar transistor (IGBT) structure including a substrate and a first gated PNPN diode is provided. The first gated PNPN diode is located on the substrate. The first gated PNPN diode includes a first gate, a first source/drain extension (SDE) region, and a second SDE region. The first gate is located on the substrate. The first SDE region and the second SDE region are located in the substrate on two sides of the first gate.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: April 26, 2022
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chun-Sheng Chen, Yen-Cheng Fang, Zih-Han Chen