Abstract: An image sensor may include a substrate including a plurality of unit pixel regions and having first and second surfaces facing each other. Each of the unit pixel regions may include a plurality of floating diffusion parts spaced apart from each other in the substrate, storage nodes provided in the substrate to be spaced apart from and facing the floating diffusion parts, a transfer gate adjacent to a region between the floating diffusion parts and the storage nodes, and photoelectric conversion parts sequentially stacked on one of the first and second surfaces. Each of the photoelectric conversion parts may include common and pixel electrodes respectively provided on top and bottom surfaces thereof and each pixel electrode may be electrically connected to a corresponding one of the storage nodes.

Abstract: A display device and a manufacturing method of a display device are provided. The display device includes a substrate, a plurality of first light-emitting elements, and at least one second light-emitting element. The first light-emitting elements are arranged on the substrate. A plurality of first electrodes are provided on a surface of each of the first light-emitting elements facing away from the substrate. The second light-emitting element is disposed on the substrate. A plurality of second electrodes are provided on a surface of the second light-emitting element facing away from the substrate. An orthographic projection of the second light-emitting element on the substrate partially overlaps orthographic projections of the first light-emitting elements on the substrate.

Abstract: Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad having a larger diameter or surface area (e.g., oversized for the application) may be used when a contact pad is positioned over a TSV in one or both substrates.

Abstract: A silicon carbide semiconductor device includes: a silicon carbide semiconductor substrate that has a front surface and a rear surface; and a plurality of ohmic electrodes that are in ohmic contact with a surface of silicon carbide on at least one of the front surface and the rear surface of the silicon carbide semiconductor substrate. The plurality of ohmic electrodes are scattered on the surface of the silicon carbide to provide a concavity and convexity. The concavity and convexity has a height due to the ohmic electrodes less than 1.0 ?m.

Abstract: An overlay metrology target (T) is formed by a lithographic process. A first image (740(0)) of the target structure is obtained using with illuminating radiation having a first angular distribution, the first image being formed using radiation diffracted in a first direction (X) and radiation diffracted in a second direction (Y). A second image (740(R)) of the target structure using illuminating radiation having a second angular illumination distribution which the same as the first angular distribution, but rotated 90 degrees. The first image and the second image can be used together so as to discriminate between radiation diffracted in the first direction and radiation diffracted in the second direction by the same part of the target structure. This discrimination allows overlay and other asymmetry-related properties to be measured independently in X and Y, even in the presence of two-dimensional structures within the same part of the target structure.

Abstract: A substrate includes a photoelectric converting unit in a pixel unit and a reflection ratio adjusting layer provided on the substrate in an incident direction of incident light with respect to the substrate for adjusting reflection of the incident light on the substrate. The reflection ratio adjusting layer includes a first layer formed on the substrate and a second layer formed on the first layer, the first layer has an uneven structure provided on the substrate, and a recess portion on the uneven structure is filled with a material having a lower refractive index than that of the substrate forming the second layer, and a thickness of the first layer is optimized for a wavelength of light to be received. The present technology may be applied to an imaging device.

Abstract: A packaging unit, a component packaging structure and a preparation method thereof. The packaging unit includes a bonding substrate and spacers formed on the bonding substrate through a patterning process, wherein the bonding substrate is reserved with packaging regions for applying sealant. When the packaging unit is used to package a component, because the spacer(s) is supported between the bonding substrate and the base substrate, the packaging unit is easy to separate from the base substrate At the same time, the packaging unit has little or no damage to the base substrate and elements formed on the base substrate, thus effectively protecting the performance of the base substrate and the elements on the base substrate.

Abstract: The present disclosure relates to a semiconductor chip scale package including a semiconductor die. The semiconductor die has a first major surface opposing a second major surface, a plurality of side walls extending between the first major surface and second major surface, a plurality of electrical contacts arranged on the second major surface of the semiconductor die, and an insulating material disposed on the plurality of side walls and on the first major surface. The insulating material includes a machine readable identifier by which a semiconductor chip scale packaging type is identifiable by an identification apparatus that reads the machine readable identifier, and the machine readable identifier includes a colour component.

Abstract: Representative implementations provide techniques for processing integrated circuit (IC) dies and related devices, in preparation for stacking and bonding the devices. The disclosed techniques provide removal of processing residue from the device surfaces while protecting the underlying layers. One or more sacrificial layers may be applied to a surface of the device during processing to protect the underlying layers. Processing residue is attached to the sacrificial layers instead of the device, and can be removed with the sacrificial layers.

Abstract: Fabrication of an alignment mark in a semiconductor device is simplified. A semiconductor device including a semiconductor substrate, an epitaxial layer, and an alignment mark is provided. The epitaxial layer included in the semiconductor device includes a single-crystalline semiconductor that is epitaxially grown on a surface of the semiconductor substrate included in the semiconductor device. The alignment mark included in the semiconductor device is disposed between the semiconductor substrate and the epitaxial layer.

Abstract: The backside illuminated image sensor comprises a substrate of semiconductor material, detector elements arranged at a main surface, a dielectric layer on or above the main surface, a first capacitor layer and a second capacitor layer above the main surface, the capacitor layers forming a capacitor (C1, C2). A peripheral circuit is integrated in the substrate apart from the detector elements, the peripheral circuit being configured for one or more operations of the group consisting of voltage regulation, charge pump operation and stabilization of clock generation, and the capacitor layers are electrically connected with contact regions of the peripheral circuit.

Abstract: An insulated gate bipolar transistor (IGBT) structure including a substrate and a first gated PNPN diode is provided. The first gated PNPN diode is located on the substrate. The first gated PNPN diode includes a first gate, a first source/drain extension (SDE) region, and a second SDE region. The first gate is located on the substrate. The first SDE region and the second SDE region are located in the substrate on two sides of the first gate.

Abstract: A chip on film and a display device are disclosed. One connection end of the chip on film is disposed with a pin to be compatible to at least one plug interface disposed at a connection end of a flexible printed circuit board. A pin connect method in which the pin and the plug interface are matched is adopted in the connection between the flexible printed circuit board and the chip on film, which optimizes the bonding process between the flexible printed circuit board and the chip on film and saves material cost and equipment cost required for thermal-compression of the anisotropic conductive film.

Abstract: Methods of fabricating and using an overlay mark are provided. In some embodiments, the overlay mark includes an upper layer and a lower layer disposed below the upper layer. The lower layer includes a first plurality of compound gratings extending in a first direction and disposed in a first region of the overlay mark, each of the first plurality of compound gratings including one first element and at least two second elements disposed on one side of the first element, and a second plurality of compound gratings extending the first direction and disposed in a second region of the overlay mark, each of the second plurality of compound gratings including one third element and at least two fourth elements on one side of the third element. The first plurality of compound gratings is a mirror image of the second plurality of compound gratings.

Abstract: The present invention provides a substrate and a method for monitoring positions of boundaries of a film layer disposed on a substrate. A plurality of sets of positioning units are provided in a non-display region of the substrate. Each set of the positioning units includes at least two primary positioning marks and corresponding primary positioning rulers. There are at least two secondary positioning marks and corresponding secondary positioning rulers disposed between the two adjacent primary positioning marks. The present invention determines a specific position of the boundaries of the film layer according to readings of the positioning rulers of the plurality of sets of positioning units corresponding to the boundaries of the film layer.

Abstract: A display substrate includes: a base substrate including a photosensitive region, the photosensitive region including a plurality of display regions spaced apart and a gap region between the plurality of display regions; a first electrode layer on the base substrate; a light-emitting layer on a side of the first electrode layer away from the base substrate; and a second electrode layer on a side of the light-emitting layer away from the base substrate. Each display region corresponds to at least one first luminescent material region of the light-emitting layer; the gap region corresponds to the plurality of second luminescent material regions of the light-emitting layer; a part of the second electrode layer in the photosensitive region includes a plurality of second electrodes spaced apart, and an orthographic projection of each second electrode on the base substrate overlaps with each display region.

Abstract: A semiconductor device includes: a substrate; a drift region disposed on a principal surface of the substrate; a first well region extending from a second principal surface of the drift region in a direction perpendicular to the second principal surface and having a bottom portion; a second well region being in contact with the bottom portion and disposed at a portion inside the substrate located below the bottom portion; and a source region extending in a perpendicular direction from a region of the second principal surface provided with the first well region, and reaching the second well region. In a direction parallel to the second principal surface and oriented from a source electrode to a drain electrode, a distance of the second well region in contact with a gate insulating film is shorter than a distance of the first well region in contact with the gate insulating film.

Abstract: Methods and structures for improving alignment contrast for patterning a metal layer generally includes depositing a metal layer having a plurality of grains, wherein grain boundaries between the grains forms grooves at a surface of the metal layer. The metal layer is subjected to surface treatment to form an oxide or a nitride layer and fill the surface grooves. The metal layer can be patterned using alignment marks in the metal layer and/or underlying layers. Filling the grooves with the oxide or nitride increases alignment contrast relative to patterning the metal layer without the surface treating.

Abstract: A semiconductor structure includes an electrode element with an upper surface. The upper surface includes at least one convex curved portion.

Abstract: A light emitting device includes a backplane, an array of light emitting diodes attached to a front side of the backplane, a transparent conductive layer contacting front side surfaces of the light emitting diodes, an optical bonding layer located over a front side surface of the transparent conductive layer, a transparent cover plate located over a front side surface of the optical bonding layer, and a black matrix layer including an array of openings therethrough, and located between the optical bonding layer and the transparent cover plate.