Abstract: The present invention relates to a method of manufacturing a semiconductor device having an excellent gettering effect. In this method, when phosphorus is added to a poly-Si film, which has been crystallized by the addition of a metal, to subject the resultant poly-Si film to the heat treatment to carry out gettering therefor, the device is performed for the shape of the island-like insulating film on the poly-Si film which is employed when implanting phosphorus. Thereby, the area of the boundary surface between the region to which phosphorus has been added and the region to which no phosphorus has been added is increased to enhance gettering efficiency.

Abstract: Methods for making thin silicon layers suspended over recesses in glass wafers or substrates are disclosed. The suspended silicon wafers can be thin and flat, and can be made using methods not requiring heavy doping or wet chemical etching of the silicon. Devices suitable for production using methods according to the invention include tuning forks, combs, beams, inertial devices, and gyroscopes. One embodiment of the present invention includes providing a thin silicon wafer, and a glass wafer or substrate. Recesses are formed in one surface of the glass wafer, and electrodes are formed in the recesses. The silicon wafer is then bonded to the glass wafer over the recesses. The silicon wafer is them etched to impart the desired suspended or silicon wafer structure. In another embodiment of the present invention, the silicon wafer has a patterned metal layer. The silicon wafer is bonded to the glass wafer, with the patterned metal layer positioned adjacent the recesses in the glass wafer.

Abstract: A process for creating a broadly tunable Distributed Bragg Reflector (DBR) with a reduced recombination rate. According to the current invention, this may be achieved by creating electron confinement regions and hole confinement regions in the waveguide of the DBR. Preferably, this is achieved by engineering the band gaps of the DBR waveguide and cladding materials. Preferably, the materials selected for use in the DBR may be lattice matched. Alternately, two or more thin electron confinement regions and two or more thin hole confinement regions may be created to take advantage of strain compensation in thinner layers thereby broadening the choices of materials appropriate for use in creating a broadly tunable DBR. Alternately, graded materials and/or graded interfaces may be created according to alternate processes according to the current invention to provide effective electron and/or hole confinement regions in various DBR designs.

Abstract: A semiconductor device with high reliability is provided using an SOI substrate. When the SOI substrate is fabricated by using a technique typified by SIMOX, ELTRAN, or Smart-Cut, a single crystal semiconductor substrate having a main surface (crystal face) of a {110} plane is used. In such an SOI substrate, adhesion between a buried insulating layer as an under layer and a single crystal silicon layer is high, and it becomes possible to realize a semiconductor device with high reliability.

Abstract: Systems and methods are described for synthesis of films, coatings or layers using precursor exerted pressure containment. A method includes exerting a pressure between a first precursor layer that is coupled to a first substrate and a second precursor layer that is coupled to a second substrate; forming a composition layer; and moving the first substrate relative to the second substrate, wherein the composition layer remains coupled to the second substrate.

Abstract: A method is provided for forming one or more doped layers using ion-implantation in the fabrication of thyristor devices. For example, these thyristors may be made from single crystalline silicon carbide. According to one aspect of the invention, one of the required layers is formed by introducing dopants after crystal growth as opposed to conventional methods which involve doping during crystal growth. Specifically, impurities may be introduced by using the technique of ion implantation.

Abstract: Deep reactive ion etching creates a single mask MEMS structure 20-50 &eegr;m deep on the top surface of a wafer. Thereafter, a bottom surface etch cooperates with trenches formed in the MEMS structure to provide through trenches which release large area structures of arbitrary shape and having a thickness up to that of the wafer. The released structure is supported in the wafer by MEMS support beams and motion is detected and affected by MEMS sensors and actuators, respectively.

Abstract: To provide a laser apparatus and a laser annealing method with which a crystalline semiconductor film with a larger crystal grain size is obtained and which are low in their running cost. A solid state laser easy to maintenance and high in durability is used as a laser, and laser light emitted therefrom is linearized to increase the throughput and to reduce the production cost as a whole. Further, both the front side and the back side of an amorphous semiconductor film is irradiated with such laser light to obtain the crystalline semiconductor film with a larger crystal grain size.

Abstract: A linear laser light which has an energy and is to be scanned is irradiated to a semiconductor device formed on a substrate, and then the substrate is rotated to irradiate to the semiconductor device a linear laser light which has a higher energy than that of the irradiated linear laser light and is to be scanned. Also, in a semiconductor device having an analog circuit region and a remaining circuit region wherein the analog circuit region is smaller than the remaining circuit region, a linear laser light having an irradiation area is irradiated to the analog circuit region without moving the irradiation area so as not to overlap the laser lights by scanning. On the other hand, the linear laser light to be scanned is irradiated to the remaining circuit region.

Abstract: Systems and methods are described for synthesis of films, coatings or layers using precursor exerted pressure containment. A method includes exerting a pressure between a first precursor layer that is coupled to a first substrate and a second precursor layer that is coupled to a second substrate; forming a composition layer; and moving the first substrate relative to the second substrate, wherein the composition layer remains coupled to the second substrate.

Abstract: A tunable Fabry-Perot filter, which includes a pair of opposed partially reflective surfaces, a cavity between the partially reflective surfaces, a nano-dispersion of liquid crystals disposed in the cavity, and a control unit for applying an electric field to the liquid crystals.

Abstract: A method of fabricating a self-aligned vertical combdrive is described. The method includes the steps of etching in a semiconductor wafer a first comb with a coarse set of teeth. A second semiconductor wafer is bonded to the first set of teeth. A set of accurately positioned teeth is etched in the second wafer with teeth overlapping the teeth in the first comb. The lower teeth are etched using the overlapping teeth as a mask to assure proper alignment. One variation in this fabrication method whereby the first coarse comb teeth are etched on semiconductor-on-insulator instead, allows creation of double-sided comb actuators with increased torsional deflection range. Another variation to this fabrication method that keeps the electrically isolated upper masking teeth allows creation of dual-mode vertical comb actuators after an initial assembly step.

Abstract: A p channel thin-film transistor (TFT) made of directly deposited microcrystalline silicon (uc-Si). The p TFT is integrated with its n channel counterpart on a single uc-Si film, to form a complementary metal-silicon oxide-silicon (CMOS) inverter of deposited uc-Si. The uc-Si channel material can be grown at lower temperatures by plasma-enhanced chemical vapor deposition in a process similar to the deposition. The p and n channels share the same uc-Si layer. The Figure shows the processing steps of manufacturing the TFT, where (12) represents the uc-Si layer of the device.

Abstract: A method for manufacturing a semiconductor device having a movable unit includes a step of forming an SOI substrate that includes a semiconductor substrate, an insulating layer, and a semiconductor layer. The method further includes a step of dry etching the semiconductor layer to form a trench and a step of dry etching a sidewall defining the trench at a portion adjacent to a bottom of the trench to form the movable unit. The later dry etching is implemented with a charge building up on a surface of the insulating layer that is exposed during the former dry etching to etch the portion. In addition, the later dry etching is implemented at an etching rate higher than that at which the former dry etching is implemented to reduce the deposition amount of a protection film deposited on a reverse side of the movable unit during the later dry etching.

Abstract: A method of fabricating an image sensor having pin photodiodes residing vertically atop underlying CMOS control circuitry. In the preferred technique, pin photodiodes fabricated in amorphous silicon are utilized.

Abstract: Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm.

Abstract: A method of fabricating a semiconductor structure including the steps of: providing a silicon substrate having a surface; forming by atomic layer deposition a monocrystalline seed layer on the surface of the silicon substrate; and forming by atomic layer deposition one or more layers of a monocrystalline high dielectric constant oxide on the seed layer, where providing a substrate includes providing a substrate having formed thereon a silicon oxide, and wherein forming by atomic layer deposition a seed layer further includes depositing a layer of a metal oxide onto a surface of the silicon oxide, flushing the layer of metal oxide with an inert gas, and reacting the metal oxide and the silicon oxide to form a monocrystalline silicate.

Abstract: An IGBT is formed in a thin (less than 250 microns thick) float zone silicon wafer using a hydrogen implant to form an N+ buffer layer at the bottom of the wafer. A weak anode is formed on the bottom of the wafer. A single hydrogen implant, or a plurality of hydrogen implants of progressively shallower depth and increasing dose can be used to form the implant in a diffused float zone wafer. The process may also be used to form an N+ contact region in silicon to permit a good ohmic contact to the silicon for any type device.

Abstract: The present invention relates to a pinned photodiode for an image sensor and a method for manufacturing the same; and, more particularly, to a pinned photodiode of an image sensor fabricated by CMOS processes and a manufacturing method thereof The pinned photodiode, according to an embodiment of the present invention, includes a semiconductor layer of a first conductivity type; and at least two first doping regions of a second conductivity type alternately formed in the semiconductor layer and connected to each other at edges thereof so that the first doping regions have the same potential, wherein a plurality of PN junctions is formed in the semiconductor layer and the PN junctions improves a capturing capacity of photoelectric charges generated in the photodiode.

Abstract: The present invention provides an optoelectronic device, a method of manufacture thereof and an integrated optoelectronic system incorporating the same. The optoelectronic device may be a tunable laser that includes a capacitor located over one of the first outer surface or the second outer surface. The outer metal layers of the tunable laser can be used to form a first electrode of the laser, after which a dielectric layer and a second electrode are deposited and patterned to form the laser having a capacitor incorporated thereon.