Abstract: The present invention is a method for integrating an anti-reflection layer and a salicide block. The method comprises the following steps: A substrate is provided that is divided into at least a sensor area and a transistor area, wherein the sensor area comprises a doped region and the transistor area comprises a transistor that includes a gate, a source and a drain; forming a composite layer on the substrate, wherein the composite layer at least also covers both the sensor area and the transistor area, and the composite layer increases the refractive index of light that propagates from the doped region into the composite layer; performing an etching process and a photolithography process to remove part of the composite layer and to let top of the gate, the source and the drain are not covered by the composite layer; and performing a salicide process to let top of the gate, the source and the drain are covered by a silicate.

Abstract: An electrical device such as a diode usable in high voltage applications wherein the electrical device is fabricated from a method which yields a plurality of high voltage electrical devices, the present method including providing a substrate of a semiconductor material having a predetermined substrate conductive type, the substrate being typically formed from a monocrystalline growth method, forming a second epitaxial layer contiguous with the upper surface of the substrate, the epitaxial layer having a predetermined second layer conductive type, and thereafter forming a top layer of dopant, material in a predetermined pattern upon the upper surface of the second epitaxial layer. This predetermined pattern of dopant material typically takes the form of an array of patches which can be achieved through either a masking and etching process, or through a screen printing process.

Abstract: An electrical isolation method for silicon microelectromechanical systems provides trenches filled with insulation layers that support released silicon structures. The insulation layer that fills the trenches passes through the middle portion of the electrodes, anchors the electrodes to the silicon substrate and supports the electrode. The insulation layers do not attach the electrode to the sidewalls of the substrate, thereby forming an electrode having an “island” shape. Such an electrode is spaced far apart from the adjacent walls of the silicon substrate providing a small parasitic capacitance for the resulting structure. The isolation method is consistent with fabricating a complex structure or a structure with a complicated electrode arrangement. Furthermore, the structure and the electrode are separated from the silicon substrate in a single release step.

Abstract: An improved method and structure for a transistor device with a lateral drift region and a conducting top field plate is presented. The method consists of decreasing the gate to drain capacitance by means of decreasing the portion of the field plate that is connected to the gate electrode, and hence the effective overlap of the gate with the drift region and drain. This results in decreased energy dissipation in switching the transistor, and more efficient operation. The rate of decrease of the gate to drain capacitance is even faster at higher drain voltages, inuring in significant energy efficiencies in high voltage applications.

Abstract: The present invention provides for a method and an apparatus for implementing corrected species by monitoring state parameters in a manufacturing process. A process run of semiconductor devices is performed. Production data relating to the process run of semiconductor devices is acquired. The acquired production data is stored into a production database. A recipe management analysis is performed. The apparatus of the present invention comprises: a recipe management system; a first machine interface connected to said recipe management system; a processing tool connected to said first machine interface; and a fault detection system connected to said first machine interface.

Abstract: A method is provided to form a LOCOS isolation in a CMOS SOI device. The SOI has a top silicon layer, a bottom silicon layer, and an insulation layer between the top and bottom silicon layers. An oxide layer is formed over the top silicon layer, and an LPCVD layer is deposited over the oxide layer. A photoresist is provided over the LPCVD layer that exposes a localized area of the LPCVD layer. The LPCVD layer and the oxide layer are etched away through the localized area to expose the top silicon layer. The silicon in the top silicon layer is etched so as to form a recess in the top silicon layer. The photoresist is removed and an isolation oxide is grown over the silicon in the recess so that the silicon in the recess is fully oxidized.

Abstract: The specification describes interconnection techniques for interconnecting large arrays of micromechanical devices on a silicon platform. Interconnections are routed through vias extending through the thickness of the substrate. The vias are formed by etching holes through the silicon wafer, depositing an insulating layer on the sidewalls of the holes, depositing a barrier layer on the insulating layer, electrolytically depositing a metal selected from the group consisting of copper and nickel to form via plugs in the holes, and depositing another barrier layer over the via plugs. It is found that electrolytic deposition will successfully plug the holes even when the aspect ratio of the through holes is greater than four and the hole diameter less than 100 microns.

Abstract: The invention relates to a wiring method for vertical system integration. According to the method described in the invention, the individual component layers in different substrates are first processed independently of each other in accordance with the state of the art (DE 44 33 846 A1) and then assembled. First, via holes are opened up on the front side of the top substrate which preferably pass through all the component layers present. The top substrate is then thinned from the rear side as far as the via holes, after which a fully processed bottom substrate is joined to the top substrate. Next, the via holes are extended (so-called interchip via holes) as far as a metallized level of the bottom substrate and the contact between the top and bottom substrates is established (wiring). According to the present invention the wiring is carried out in a way which allows for a maximum density of the vertical contacts between the metallization of the top substrate and that of the bottom substrate.

Abstract: Apparatus for a micro-electro-mechanical switch that provides single pole, double throw switching action. The switch comprises a single RF input line and two RF output lines. The switch additionally comprises two armatures, each mechanically connected to a substrate at one end and having a conducting transmission line at the other end with a suspended biasing electrode located on top of or within a structural layer of the armature. Each conducting transmission line has conducting dimples that protrude beyond the bottom of the armature carrying the conducting transmission line. Closure of an armature causes the dimples of the corresponding conducting transmission line to mechanically and electrically engage the RF input line and the corresponding RF output line, thus directing RF energy from the RF input line to the selected RF output line.

Abstract: A thin film transistor display is formed on a substrate having a first region and a second region. The first region includes a transistor area, and the second region includes a pad area. A gate electrode is first formed in the transistor area, and a pad electrode is formed in the pad area. An insulating layer, a semiconductor layer, and a doped silicon layer are formed on the substrate. An opening is formed in the pad area to expose the pad electrode. A channel is defined in the transistor area. A source and a drain electrode are formed and are separated by the channel. The substrate is exposed at a first side area of the first region and exposed in the second region except the pad area.

Abstract: The present invention provides a novel thermoelectric semiconductor material having excellent thermoelectric property which is not lowered like a conventional PbTe-based or PbSnTe-based semiconductor material even if a strength is improved by sintering. The thermoelectric semiconductor material of the invention is characterized by having chemical formula AB2X4 (where, A is a simple substance or mixture of Pb, Sn and Ge (IV family elements), B is a simple substance or mixture of Bi and Sb (V family elements), and X is a simple substance or mixture of Te and Se (VI family elements). In this case, a spark plasma sintering device is used to apply a pulsed current through the powder material to cause an electrical discharge among particles of the powder to synthesize the compound AB2X4 having a uniform structure. And, the invention synthesizes a compound, which is to be a thermoelectric semiconductor material, so to have a uniform structure.

Abstract: A novel structure of an active electro-optical device is disclosed. The device is provided with complementary thin film insulated gate field effect transistors (TFTs) therein which comprise a P-TFT and an N-TFT. P-TFT and N-TFT are connected to a common signal line by the gate electrodes thereof, while the source (or drain) electrodes thereof are connected to a common signal line as a well as to one of the picture element electrodes. In case of driving the active electro-optical device, a gradation display can be carried out in a driving method having a display timing determined in relation to a time F for writing one screen and a time (t) for writing in one picture element, by applying a reference signal in a cycle of the time (t), to the signal line used for a certain picture element driving selection, and by applying the select signal to the other signal line at a certain timing within the time (t), and whereby setting the value of the voltage to be applied to a liquid crystal.

Abstract: A gate oxide film 18 and a gate electrode 20 are formed on a surface of a P-type substrate 14. A concave portion 42 is provided in a region of the P-type substrate 14, the region being contiguous to the gate electrode 20. On the P-type substrate 14, an N-type drain region 30 is disposed on the opposite side of the gate electrode 20 from the concave portion 42. N-type impurities are implanted into the P-type substrate 14 at a predetermined angle relative to the latter, thereby forming an N-type region 44 which includes a region underneath the concave portion 42 and which is partially submerged beneath the gate oxide film 18. P-type impurities are then implanted into the P-type substrate 14 at right angles to the latter, thus forming a P-type region 46 which includes a region underneath the concave portion 42 while covering the N-type region 44 and which forms a PN junction diode in combination with the N-type region 44.

Abstract: Performance-enhancing, reduced-area metalization adhesion areas in force-sensing transducers are described.

Abstract: A plurality of pressure sensor dice are attached to an array of pressure sensor die attach sites located on a substrate. The pressure sensor dice are then electrically connected to the pressure sensor die attach sites using standard wire bond techniques. The resulting array of pressure sensor sub-assemblies is then molded, using a mold tool which closes on three sides of the substrate so that a cavity is formed that is open on the fourth side. A portion of the outer surface of the micro-machine element of each pressure sensor die is left exposed at the bottom of a cavity or hole in the encapsulant. After molding, the exposed outer surface of the micro-machine element is covered with a pressure coupling gel applied in the cavity. The resulting array of packaged pressure sensors are then sigulated using well know sawing or laser techniques or by snapping a specially formed snap array.

Abstract: An object of the present invention is to firmly attach a metallic fixing member to which an optical-fiber member is fixed, to a substrate. A tubular metallic fixing member, to one end of which an optical-fiber member is connected, is brazed and attached to a substrate housing a photosemiconductor element by depositing a nickel plating layer and a gold plating layer in succession on the surface thereof, subjecting the metallic fixing member into which a light-transmitting member is attached via glass, to an etching treatment, and removing nickel oxide formed on the surface of the gold plating layer.

Abstract: A method of manufacturing a semiconductor component includes disposing a layer (120) of an electrically insulative material over a semiconductor substrate (110), etching a trench (310) into the layer and the semiconductor substrate, disposing a layer (410) of a semiconductor material in the trench, and forming a gate contact (1410) in the trench.

Abstract: A method of fabricating a light emitting device includes providing a light emitting diode that emits primary light, and locating proximate to the light emitting diode a (Sr1−u−v−xMguCavBax)(Ga2−y−zAlyInzS4):Eu2+ phosphor material capable of absorbing at least a portion of the primary light and emitting secondary light having a wavelength longer than a wavelength of the primary light. The composition of the phosphor material can be selected to determine the wavelengths of the secondary light. In one embodiment, the light emitting device includes the phosphor material dispersed as phosphor particles in another material disposed around the light emitting diode. In another embodiment, the light emitting device includes the phosphor material deposited as a phosphor film on at least one surface of the light emitting diode.

Abstract: Presented is a process for manufacturing circuit structures of the SOI type integrated on a semiconductor substrate having a first type of conductivity. The process includes forming at least one well with a second type of conductivity in the semiconductor substrate and forming a hole within the well. The hole is then coated with an insulating coating layer, and an opening is formed through the insulating coating layer at the bottom of the hole. The hole is then filled with an epitaxial layer grown from a seed that was made accessible through the opening in the hole.

Abstract: A MEMS thermal actuator device is provided that is capable of providing linear displacement in a plane generally parallel to the surface of a substrate. Additionally, the MEMS thermal actuator of the present invention may provide for a self-contained heating mechanism that allows for the thermal actuator to be actuated using lower power consumption and lower operating temperatures. The MEMS thermal actuator includes a microelectronic substrate having a first surface and at least one anchor structure affixed to the first surface. A composite beam extends from the anchor(s) and overlies the first surface of the substrate. The composite beam is adapted for thermal actuation, such that it will controllably deflect along a predetermined path that extends substantially parallel to the first surface of the microelectronic substrate. In one embodiment the composite beam comprises two or layers having materials that have correspondingly different thermal coefficients of expansion.