Abstract: A method is provided that automatically generates compensated semiconductor devices based on existing VLSI CAD database circuit designs. The preferred method forms a plurality of edge projection shapes which are intersected with active area shapes to form gate edge shapes. The gate edge shapes and residual of the edge shapes are the sorted according to their relative position. These shapes are then selectively biased according to their relative position, and then are used to compensate the existing gate conductor shapes. Thus, this method provides a way to generate gate structures with compensated gate lengths for n-channel and p-channel devices based on existing gate, diffusion and implant designs. This system has the advantage of generating designs with detailed attention to the placement and minimization of jogs that negatively impact the lithography performance.

Abstract: A method for designing an automotive vehicle body shape having fixed and free boundaries to meet a pre-specified velocity or pressure distribution for a portion of the vehicle body migrates a set of vortex elements, whose strengths are related to the desired velocity and pressure distributions, until they reach spatial positions consistent with the desired velocity and pressure profile. A desired velocity and pressure profile is specified for a first portion and a shape is specified for a second portion of the vehicle body, and an initial shape for the first portion is estimated having a free surface cross-section, which is divided into free surface elements. Free surface vorticies are assigned in one-to-one correspondence to the free surface elements, and fixed surface vorticies in one-to-one correspondence with the fixed surface elements are determined.

Abstract: The present invention is a novel system that allows the user to create, modify, or delete a configurator using templates. Once the configurator is constructed, the present invention allows the user to generate specific configurations using the constructed configurator. Templates are objects that are created by the configurator generator and recognized and used by the configurator to create configurations. Templates are stored in a persistent storage area of the configurator generator and are recalled when a change or deletion to the resulting configurator is desired. The configurator generator provides the user with a simple, intuitive, and computer assisted way of producing or modifying templates. A user defines a specific domain that describes an end product through a graphical interface of the system thereby creating a set of templates. The system then takes the user-defined templates to create configurations of the end product.

Abstract: An electronic device, such as an integrated circuit, is provided with elements, all of which are never used in a single application. These elements are not absolutely decoys or dummys, although this is a possibility. For a particular application, the elements are so chosen that, in conjunction with a supplementary logic package, they provide the desired functions. The logic elements used as well as the functions of the main logic package of the device are determined by the supplementary logic. The combined logic is in no way determined by coding or decoding; this logic is specific and both parts together form an electronic component or device. The complete logic is therefore similar to a hybrid circuit but without the wired connections. If this device is compromised to an enemy or a business competitor, the main logic package or packages of the the device need not be newly developed; only the supplementary logic package or packages must be replaced.

Abstract: A system for optimally locating cells on the surface of an integrated circuit chip is presented herein. The system comprises constructing a plurality of neighborhoods containing elements positionally related to one another; initially evaluating the lowest level of region hierarchy; iteratively developing a logical one-dimensional preplacement of elements on said surface; performing an affinity driven discrete preplacement optimization; evaluating whether a highest level of regional hierarchy has been attained; iteratively performing a dispersion driven spring system to levelize cell density and an unconstrained sinusoidal optimization; executing a density levelizing procedure; iteratively optimizing while controlling element densities; removing element overlap; iteratively optimizing for desired spacing between elements, adjusting element spacing, and permuting elements; locating elements on grid lines; and iteratively performing a functional sieve crystallization.

Abstract: A simulation apparatus for a semiconductor integrated circuit is provided that includes model preparing device, logic simulating device and power supply voltage drop simulating device. The model preparing device prepares a feeder system model including current sources that correspond to respective circuit elements constituting a circuit to be designed, and power supply wiring and ground wiring for applying voltage to the current sources, on the basis of a result of automatic layout of the circuit. The logic simulating device implements logic simulation of the circuit, and outputs event information related to the circuit elements which have undergone a change of a condition thereof. The power supply voltage drop simulating device implements simulation while driving the current sources in the feeder system model that correspond to the circuit elements listed in the event information, and computing voltage drop in the power supply wiring and the ground wiring.

Abstract: Methods of speeding error analysis of electronic devices under test using simulation software that has the capability of simultaneously executing up to 32 tests on one image of the design model. One embodiment of the method contemplates executing the tests staggered in time so that a larger portion of the test is available for examination and execution at any given time. This allows errors to be found more quickly. Another embodiment contemplates more quickly testing a device initialization sequence by randomly establishing values for each state device, separately for each of the 32 tests, running the simulation, and then determining whether the state device values converge.

Abstract: A system for optimizing the density of cells located on a surface of a semiconductor chip divided into a plurality of rectangular regions is provided herein. The corners of these regions define nodes. The system comprises computing an average local cell density for regions adjacent to each node and deforming these regions by relocating nodes to positions that minimize a cost function associated with the densities of the new deformed regions bordering the relocated nodes.

Abstract: An incremental circuit design methodology using logic synthesis where comparisons are made between netlists corresponding to two separate versions of a design to determine similarities between the two. The similarities are then used to ensure the same physical implementation for the unchanged portion of the design. Therefore, information from the physical implementation of the previous design may be used in implementing the later design.

Abstract: A byte swapping device includes first and second data ports and data path logic coupled between the first and second data ports. The byte swapping device is employed in a data processing system comprising a data storage device configured to store bytes of data, a processor which reads data from the data storage device and writes data to the data storage device, and the byte swapping device coupled between the data storage device and the processor. The first data port is coupled to the data storage device and the second data port is coupled to the processor. The storage device is typically a system memory or peripheral device controller. The processor processes data in a first endian format, i.e., big-endian or little-endian format, and at least a portion of the data stored in the data storage device is in the opposite byte ordering. The byte swapping device selectively byte swaps data transferred between the processor and storage device.

Abstract: A system for interactive design and simulation of an electronic circuit allowing a user to design a circuit by graphical entry and to view full or partial simulation and design results simultaneously, on a single display window. The user is able to define the form of a display of speed, delay, loading, symbols, simulation input and/or output values on each node and any path of the design. Simulation may be user-defined or other process time. The user is further able to view any information relevant to any object in the design at any level of design abstraction, and is able to view multiple levels of design abstraction simultaneously and to display information common to the various representations.

Abstract: A system for ascertaining the penalty associated with relocating a cell located on a surface of a semiconductor chip to an alternate location is disclosed herein. The system comprises a region capacity calculator for determining a capacity of cells which will fit in the current region, a height capacity calculator for determining the sum of heights for all cells located in each region, a basic penalty calculator which computes a basic penalty associated with relocating the cell to another location based on the capacity and heights of cells for the current region and the capacity and heights of cells in the proposed region, and a total penalty calculator for computing the total penalty associated with the basic penalty, penalties associated with multiple regions, and cell capacity for the current cell.

Abstract: A map display apparatus for a motor vehicle comprising: road map storage device which stores road map data relating to a road map; a display device capable of displaying the road map; bird's-eye view data converting circuit which converts the road map data into bird's-eye view data so that a bird's-eye view taken by obliquely looking down the road map from above is displayed on the display device; and display control circuit which displays a plurality of grid lines such that the grid lines are superposed on the bird's-eye view.

Abstract: One CKD track on a direct-access storage device is divided into a plurality of fixed-length FBA blocks, only a home address HA of the CKD track and a record R0 having a CKD format are recorded in the leading FBA block, and each field (a COUNT field, KEY field and DATA field) of records R1, R2, . . . having the CKD format is recorded in the other FBA blocks. This arrangement is such that even if a format-write processing instruction for format-write from the record R1 is received from a host device, a disk control unit will not read the FBA block of HA/R0 out to a cache memory and will read out only FBA blocks from record R1 onward. As a consequence, write processing from record R1 onward can be performed in memory with ease and format-write processing can be executed at high speed.

Abstract: A system for digital simulation of an electric circuit is disclosed. The system is event-driven, and functions on a gate inversion principle, to simulate an electric circuit. According to the gate inversion principle, any gates or gate arrangements in the circuit for which the input does not change are not simulated. A machine readable circuit description is generated which includes the gates and the gate arrangements for the circuit. Translation means creates data structures suitable for simulation of the circuit. Simulation means creates a program which schedules the simulation of only those gates or gate arrangements whose outputs change value during the simulation. According to the preferred embodiment, the simulation means uses only inversions of signals from individual gates or gate arrangements to perform the simulation of the circuit. Furthermore, the translation means includes means for removing any NOT gates from the circuit, and means for collapsing all homogeneous connections in the circuit.

Abstract: The present invention provides a synchronous distributed simulation apparatus having a simulation supervising device which supervises a simulation device, and the simulation device which performs a synchronous simulation under supervision of the simulation supervising device, in which the simulation supervising device comprises counting means for counting time in simulation, time width setting means for setting a time width of simulation for each time zone where facilities are operated in a manufacturing process which is an object of the simulation in accordance with the time counted by the counting means, and transmitting means for transmitting data showing the time width set by the time width setting means to the simulation device, and the simulation device comprises receiving means for receiving the data showing the time width transmitted by the transmitting means in the simulation supervising device, discrete-event simulation means for simulating the manufacturing process in which change of a state may be

Abstract: An automated system for facilitating creation of a compatible rack-mountable component personal computer.

Abstract: A method and apparatus for displaying the placement of circuit blocks and the routing nets between the circuit blocks, in which: a large number of parts placed on a printed-circuit board or in a semiconductor integrated circuit are classified into a plurality of circuit blocks so that the circuit blocks are displayed; routing nets, in each of which a plurality of connection wires between circuit blocks are integrated expressed as one connection line, are displayed so as to be different in line width, line color or line pattern correspondingly to the number and kind of the connection wires in each routing net; the integrated connection lines are connected to input/output virtual pins provided in the respective circuit blocks; and the relations in arrangement/wiring among the circuit blocks, the integrated connection lines and the virtual pins are displayed on a display device so as to be observed easily by eyes.

Abstract: A method of estimating power for an integrated circuit based on high speed probability calculation having a high precision with considering correlation between signals may be provided. The method may be performed by calculating probability quantity accompanying to output nodes of respective logical gates, the probability quantity being represented by probability that logical values of the output nodes of respective logical gates are 1 (referred to as "signal probability" hereinafter) and probability that logical values of the output nodes of respective logical gates are changed (referred to as "switching probability" hereinafter), expanding into series a difference P.sub.e -P.sub.a between a strict value P.sub.e of the probability quantity and a value P.sub.

Abstract: A vehicle navigation system and guidance method for effectively guiding a driver through a traffic circle; the driver is given instructions to exit at the given turnoff, but if the driver misses the proper turnoff, the system does not indicate the situation as "off-route" but continues to direct the driver around the circle and then again provide the exit instruction as the proper turnoff is again approached.