Abstract: Methods and associated apparatus for simulating digital logic circuits with a general purpose computer system. A description of a digital logic circuit is converted into executable computer code. The code produced is capable of simulating the circuit's response to a large number of independent sets of circuit stimulus. The code is broken into separate modules which each simulate the circuit's operation during a particular clock phase. Loops within the code are limited in size to make efficient use of the computer's instruction cache and the data cache. Known constant nodes are propagated through the circuit before code is generated to eliminate the generation of unnecessary code. Code is only generated to simulate gates which may switch on a particular phase. Code which does not need to be evaluated during a particular phase is dropped. The circuit is broken into acyclic sets of gates and code is generated to iterate over each acyclic set of gates until stability is reached.

Abstract: A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a-high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure.

Abstract: A physical process is simulated by storing in a memory state vectors for voxels and a representation of at least one surface. The state vectors include entries that correspond to particular momentum states of set of possible momentum states at a voxel. Interaction operations are performed on the state vectors to model interactions between elements of different momentum states. In addition, surface interaction operations are performed on the representation of the surface. The surface interaction operations model interactions between the surface and elements of at least one voxel near the surface. The elements have a tangential momentum relative to the surface, and the surface interaction operations retain at least a portion of the tangential momentum of the elements. The portion of tangential momentum retained corresponds to a friction parameter. The friction parameter is varied based on changes in pressure near the surface.

Abstract: A simulation method of jaw movement comprising:a superimposing process step of reading dentition configuration data and jaw movement data, calculating a coordinate transformation matrix for matching a coordinate system of the dentition configuration data with a coordinate system in a jaw movement basic state in the jaw movement data, and transforming the dentition configuration data to coordinates on the coordinate system in the jaw movement basic state to obtain superimposed dentition configuration data; anda simulation process step of calculating superimposed dentition configuration data in another jaw movement state and superimposedly displaying a dentition configuration diagram obtained by converting the superimposed dentition configuration data to an image and a jaw movement state diagram obtained by converting the jaw movement data to an image.

Abstract: A comprehensive system and method allow an integrated circuit designer to extract accurate estimates of parasitic impedances in interconnection lines of an integrated circuit. The method includes collecting values of electrical characteristic parameters to provide a technology profile for a particular fabrication process. An Interconnect Primitive Library builder provides a collection of interconnect `primitives` that any interconnect structure fabricated under the fabrication process can be broken down into, and combines it with the technology profile for simulations in a 3-dimensional field solver to extract parameterized coupling capacitances and other characteristic impedances for each interconnect primitive. An extraction tool traces a signal path of an integrated circuit and decomposes the interconnect structures on the signal path into interconnect primitives and maps them to the Interconnect Primitive Library.

Abstract: A method of using a fet level simulator to check for races in a digital design. The method comprises varying digital design models input into the simulator. Each model comprises a clock gater circuit producing clocks with differing overlaps and dead times. Raw data files corresponding to each model input are generated by the fet level simulator. The raw data files preferably comprise lists of node values with corresponding time stamps. Corresponding latch node values in the raw data files are compared to identify the nodes of a circuit which are affected by races. Identifying affected latch nodes allows a race's root cause to be quickly pinpointed. Vector inputs to the fet level simulator may be varied. If vector inputs are varied, comparison of the raw data files comprises comparing the files generated for differing models with common vector inputs. Apparatus for implementing the above method is also disclosed.

Abstract: The hybrid adder of the present invention uses stages of carry select functions to provide serial carries and a carry look-ahead tree structure to compute the final carries in parallel. The longer the carry select stages become, the slower and smaller the hybrid adder gets by reducing the size of the carry tree. By making the carry select stages shorter, the faster and larger the adder gets by increasing the size of the carry tree. The increased flexibility of the resulting hybrid adder gives the circuit designer a greater range of possible designs to achieve optimum size and speed performance. A preferred process for selecting optimum stage lengths is also described. The method for designing the hybrid adder is preferably carried out using a logic synthesis software program.

Abstract: A system and method for entering a circuit design into a computer using a schematic capture package. The schematic capture package is modified to include a library of state flow components represented by symbols which can be connected to produce a desired representation of the circuit design. The system allows a circuit design to be displayed on a video terminal using both state flow diagram and the schematic diagram symbols, with terminals of the state flow symbols connecting to terminals of the schematic symbols. The state flow diagram using state flow symbols is combined with a schematic diagram including schematic symbols to generate a netlist representing the combined circuit.

Abstract: A circuit designing apparatus of an interactive type which enables a simplified and high-speed circuit design process while largely reducing a burden on a designer, having a speed analyzing unit for conducting a delay computation for each wiring path on a circuit to be designed and a display control unit for displaying a result of the delay computation by the speed analyzing unit on a display unit. When the speed analyzing unit conducts a delay computation, a delay value of each logic component forming the circuit that is an object of the design is set and altered according to a dullness of a signal waveform inputted to the logic component. The circuit designing apparatus of an interactive type may be applied to a system for conducting a circuit design of an integrated circuit such as an LSI or the like or a printed circuit board.

Abstract: An method for designing integrated circuits for a serial scan test using an improved, modular flip-flop cell is presented. The modular flip-flop cell has a delay element strategically placed in the serial scan chain to reduce the occurrence of hold time violations. The delay element is located in a test path along the serial scan chain. The delay element causes the hold time of the test input terminal to be non-positive, ensuring that there are no hold time violations, while not affecting the time delay on the normal data path.

Abstract: A simulation apparatus for simulating a characteristic of a semiconductor circuit, including; a distribution information input unit for receiving a distribution information, the distribution information including a range and/or profile of distribution of a variation of a device parameter and/or a process parameter of the semiconductor circuit and being adaptive to an actual distribution; a random number generating unit for generating a random number on the basis of a probability responsive to the received distribution information; a characteristic calculation unit for calculating a dominant formula by using the random number to obtain a characteristic of the semiconductor circuit; and an output unit for outputting the resultant characteristic of the semiconductor circuit.

Abstract: On determining operating conditions for a nonvolatile semiconductor memory including a MOSFET (Metal Oxide Semiconductor Field-Effect Transistor), measurement is made, before completion of manufacture of the nonvolatile semiconductor memory and after completion of manufacture of the MOSFET, of characteristics of the MOSFET to obtain parameters which are used in simulating an operation of the nonvolatile semiconductor memory. By using the parameters, simulation of the operation of the nonvolatile semiconductor memory is executed to obtain a simulation result which is preferably a result relating to deterioration of operation characteristics of the nonvolatile semiconductor memory. The operating conditions for the nonvolatile semiconductor memory are obtained from the simulation result. The nonvolatile semiconductor memory may be an EEPROM (Electrically Erasable Programmable Read-Only Memory).

Abstract: A three dimensional structure is precisely positioned at a desired location. A virtual model of the structure of interest is created and stored in a computer memory. Some time later, remote sensors are placed in selected positions on the structure of interest. The sensors are configured so as to provide real time location, attitude and orientation information regarding the structure and may consist of GPS remote units, tilt meters, gyro compasses, and pressure sensors. The position of each the remote sensors on the actual structure is also recorded in the computer memory so that the virtual model accurately reflects the configuration of the structure. As the structure is being positioned, the real-time location, attitude and orientation information produced by the remote sensors is monitored at a base station and used to update the virtual model. In this way, the virtual model accurately reflects the current location, attitude and orientation of the structure.

Abstract: An optimization apparatus comprises a hierarchical circuit specification input for entering a logic circuit having a hierarchical structure, a delay constraint input for entering delay constraints of the logic circuit, a circuit database for storing and holding the logic circuit and delay constraint, a timing analyzer for performing the timing analysis of the logic circuit, a delay constraint distributor for distributing the delay constraints to each hierarchical configuring the logic circuit according to optimization possibility of the logic circuit, an optimizing unit for performing the delay optimization of the logic circuit according to the delay constraints distributed to the respective hierarchical sub-circuit of the logic circuit, a library input for entering library information to be used for the timing analysis of the logic circuit, a library database for holding the library information, and an output for outputting the optimized logic circuit.

Abstract: Methods and associated apparatus for simulating digital logic circuits with a general purpose computer system. A description of a digital logic circuit is converted into executable computer code. The code produced is capable of simulating the circuit's response to a large number of independent sets of circuit stimulus. The code is broken into separate modules which each simulate the circuit's operation during a particular clock phase. Loops within the code are limited in size to make efficient use of the computer's instruction cache and the data cache. Known constant nodes are propagated through the circuit before code is generated to eliminate the generation of unnecessary code. Code is only generated to simulate gates which may switch on a particular phase. Code which does not need to be evaluated during a particular phase is dropped. The circuit is broken into acyclic sets of gates and code is generated to iterate over each acyclic set of gates until stability is reached.

Abstract: A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure.

Abstract: Apparatuses and methods are disclosed for determining an implant position for at least one artificial component in a joint and facilitating the implantation thereof. The apparatuses and methods include creating a joint model of a patient's joint into which an artificial component is to be implanted and creating a component model of the artificial component. The joint and artificial component models are used to simulate movement in the patient's joint with the artificial component in a test position. The component model and the joint model are used to calculate a range of motion in the joint for at least one test position based on the simulated motion. An implant position, including angular orientation, in the patient's joint is determined based on a predetermined range of motion and the calculated range of motion.

Abstract: A merchandise simulator device which allows a user to operate a desired piece of merchandise on a user's terminal as if the user was using the piece actually at hand. In the merchandise simulator device, when a workstation executes merchandise simulation software received from an HTTP server, a merchandise simulation control section is activated on the workstation to thereby display the basic image of a selected piece of merchandise in a display section. If a drag operation is carried out by a mouse of an input section, then the piece of merchandise displayed on the display section is rotated on the basis of two or more pieces of image data received from the HTTP server and also, if a mouse input is given to a button or the like of the image data displayed on the display section, then the function of the piece of merchandise displayed in the display section is simulated in whatever display state the present piece is.

Abstract: A mesh generation device comprising a boundary protective layer generating unit, a mesh point positioning unit, a triangular mesh generation unit and a triangular mesh checking unit, characterized in that the triangular mesh generating unit generates triangular meshes restrictively in the region where the boundary protective layer may be destroyed by some triangular meshes as the first stage, and generates triangular meshes in the remaining region as the second stage, and that the triangular mesh checking unit checks whether or not the generated triangular meshes are destroying the boundary protective layer after the completion of the processing in the first stage by the triangular mesh generating unit.

Abstract: A battery powered computer system monitors the address bus to determine when selected peripheral devices have not been accessed for a preset amount of time. When the preset amount of time has passed the system powers itself down and stops the system clock, placing it in a standby mode. The system is awakened by depressing a standby switch, unless there is insufficient energy in the batteries, under which circumstances an AC power source must be connected before the system can be awakened.