Abstract: An array built-in self test system has a scannable memory elements and a controller which, in combination, allow self test functions (e.g. test patterns, read/write access, and test sequences) to be modified without hardware changes to the test logic. Test sequence is controlled by logical test vectors, which can be changed, making the task of developing complex testing sequences relatively easy.

Abstract: Server fault tolerance on local area computer networks is provided by novel workstation implemented software which detects failure of a primary file server and reroutes data storage activity routed via the primary file server, to be routed via an invention-provided secondary file server. Shared file management of multiple file servers or intelligent hosts supporting a single or common high availability data storage system, for example a RAID drive, enables server or host fault tolerance to be provided for such a single highly, reliable data-storage system. Cross-mirroring in such a multi-host, high availability data storage system, along with secondary write suppression, enables server fault tolerance to be provided without significant redundant hardware costs and without a single point of failure in the data storage access paths.

Abstract: An information processing system composed of a plurality of circuit blocks operative in an normal operation mode and in a self-diagnosis mode comprises: a clock signal generating circuit for generating a basic clock signal in the normal operation mode, and a first clock signal with a period. N times (N=2, 3, . . .

Abstract: A test mode setting circuit includes a high voltage detection circuit, an uppermost row address buffer and a row address buffer control circuit for the uppermost row address buffer. When a high voltage is supplied to a common input terminal for the test mode setting, the uppermost row address buffer receives through the common input terminal an uppermost address signal, and provides the uppermost address signal as an uppermost internal row address signal.

Abstract: The present invention comprises a runt fault detector which detects positive and negative runt faults based only upon the crossings of a high voltage threshold and a low voltage threshold. Specifically, the runt fault detector detects a positive runt fault when an input signal transitions from below to above the low voltage threshold and then back below the low voltage threshold without first transitioning from below to above the high voltage threshold. The runt fault detector also detects a negative runt fault when an input signal transitions from above to below the high voltage threshold and then back above the high voltage threshold without first transitioning from above to below the low voltage threshold. Simultaneous detection of both positive and negative runt faults may also be achieved by the present invention.

Abstract: A multi-chip-module (MCM) architecture allows direct access to a chip with minimum cost in space, yield, and signal delay. A first chip of the MCM is connected to a second chip via corresponding I/Os, but only the first chip has I/Os are directly accessible off the MCM. A coupling circuit, responsive to a control signal, which passes signals in the directly accessible I/Os of the first chip to the I/Os of the second chip.

Abstract: A method of increasing the testability of sequential circuit designs with use of a clock transformation technique. Circuit states which are difficult to reach, but are nonetheless required to detect at least one fault of the circuit, are automatically identified. In accordance with one illustrative embodiment, estimations of joint line probabilities are compared with a preselected threshold value to identify hard-to-reach states. Then, commonly clocked flip-flops which must be simultaneously assigned values in order to reach the identified states are partitioned into independently clocked groups of flip-flops. In this manner, hard-to-reach circuit states are transformed into easy-to-reach states, which, in turn, results in transforming difficult-to-detect faults into easy-to-detect faults.

Abstract: A self-testing buffer circuit. The buffer circuit utilizes an adjustable delay circuit to test whether the buffer can capture a data value during a variable stroke window. The buffer includes an input circuit coupled to receive a data value generated by the self-testing buffer circuit. The buffer circuit also includes a latch which has a latch input coupled to receive the data value from the input circuit. An adjustable delay circuit having a delay adjust input is coupled to provide an adjustably delayed strobe to a clock input of the latch. A comparison circuit may be coupled to compare a latch output value to an expected value. The self-testing buffer circuit may be used in conjunction with serial or parallel test resisters to test the buffer performance for a variety of strobe delays and data values.

Abstract: The present disclosure describes a scan latch which utilizes dynamic interface nodes to facilitate full scan operation with a reduced number of transistors. A scan latch slave stage is coupled to a storage node of a storage device to capture data from that device. The scan latch slave device has an output driver with an input node coupled by a pass gate to the storage node. A scan clock line is coupled to the pass gate and to an enable input of the output driver. A slave scan clock signal received on the scan clock line enables the output driver and controls the pass gate. A master stage which may be utilized with the scan latch slave stage has a tri-state input device coupled to a serial input. The tri-state input device is controlled by a master scan clock and has an output coupled to the storage node.

Abstract: Rapid and efficient memory testing is provided by using direct memory access techniques. This hardware-based scheme operates at a considerably faster rate than a software-dependent solution running on a system's central processor.

Abstract: The scan test circuit disclosed has a first input terminal and a second input terminal for respectively inputting first data of one bit and second data as serial data, a third input terminal for inputting an operation switching signal for determining a scan operation and a normal operation, an input selector for selecting either the first data or the second data in response to the supply of the operation switching signal and outputting the selected data, a register for holding the selected data as hold data, a first output terminal for outputting first output data, and a second output terminal for outputting second output data. The scan test circuit includes a latch circuit which latches a shift mode signal and generates an operation switching latch signal. A selector selectively outputs either an input data or an input data as a selected signal in response to the supply of the signals.

Abstract: A system and method for debugging a development computing system is disclosed. The BIOS in the development system includes a debug engine. Interrupt-handling macros in BIOS include an entry macro to direct debug output codes (e.g., port 80 and beep codes) to the debug engine. A near entry macro is added to BIOS-segment macros (e.g., F000 segment) which provides the offset of the debug engine. A far entry macro is added to non-BIOS-segment macros which provides the segment and offset of the debug engine. The debug engine sends the output codes to a remote host computer via a communication channel (e.g., a bi-directional parallel port) on the development system. The debug engine also saves the contents of various registers on the development system to the host computer. Thus, the invention can be used in a stackelss environment. Debug commands (e.g., memory dump, set break address) can be issued from the host computer to the development system via the communications channel.

Abstract: An automatic data transmission rate detection circuit comprising a data detector for detecting input data in response to an external reference clock pulse, a counting circuit for up-counting the reference clock pulse, the counting circuit clearing its count upon inputting an output signal from the data detector at its clear terminal during its counting operation, a data storage unit for storing an output value from the counting circuit upon inputting the output signal from the data detector at its load enable terminal, an individual detection circuit including a plurality of individual detectors, each of the plurality of individual detectors detecting a transmission rate and an error rate of individual data in response to an output signal from the data storage unit, a density detector for detecting the entire data transmission rate in response to individual data transmission rate detect signals from the plurality of individual detectors in the individual detection circuit, and an error detector for detecting

Abstract: An integrated circuit test apparatus according to an exemplary embodiment includes a first memory section configured to store processor procedures and a second memory section configured to simultaneously store parallel integrated circuit test vectors and serial integrated circuit test vectors. A processor is coupled to the first memory section and to the second memory section. The processor is configured to execute the processor procedures to simultaneously manipulate the parallel integrated circuit test vectors and the serial integrated circuit test vectors located in the second memory to test an integrated circuit. Advantages of the invention include the ability to simultaneously store serial and parallel test vectors and to test a device under test (DUT) with simultaneous serial and parallel test vectors. The combination of serial and parallel test vectors increases performance and efficiency of the test apparatus.

Abstract: A boundary scan cell including a three-state output buffer, a test data scan flip-flop for providing an input to the three-state buffer, a control data scan flip-flop for receiving a serial control data input, independent clock signals for independently clocking the test data scan flip-flop and the control data scan flip-flop, and control circuitry for controllably providing the output of the control data scan flip-flop to the three-state output driver such that the enabled state of the three-state output buffer is controlled by the output of the control data scan flip-flop, whereby the enabled state of the three-state output driver is controlled independently of the test data in the test data scan flip-flop.

Abstract: A reset circuit for resetting a memory system following a radiation event includes an error detect circuit for producing an error signal in response to detection of an uncorrectable error in the systems memory arrays, and includes a control circuit for selectively resetting at least select portions of the memory system in response to the error detect signal. All or portions of the memory arrays can be reset by the control circuit, and complete or selective latch reset, or selective power recycling are provided. In one embodiment, the control circuit provides latch reset in response to the error detect signal so as to reset the memory latches without recycling power, and in another embodiment, the control circuit selectively cycles power to independent memory zones of the system to reset only those zones whose memory array is identified as having an uncorrectable error.

Abstract: A method for automatically testing digital electronic circuits and performing time measurements whereby a digital signal having a frequency f1 is sampled at a rate equal to f2. The sampling frequency f2 is either slightly less than or slightly greater than f1. As a result, the digital signal is sampled at either a slightly later position in time or a slightly earlier position in time during each successive period of the digital signal. After the entire interval of interest on the digital signal has been sampled, either the number of logical high data samples or the number of logical low data samples is determined. Finally, the number of data samples is multiplied by the effective time period between data samples. In this way, pulse widths on digital signals can be measured with both high resolution and good linearity. This method of time measurement may also be used to calibrate an electronic circuit tester.

Abstract: A scheme for generating test patterns for logic circuits which can generate the test patterns effectively and efficiently by making the assignments of the fewer logic values at earlier stages, so as to reduce the number of backtracking operations required.

Abstract: An EEPROM for storing multi-level data includes a memory cell array in which electrically erasable and programmable memory cells are arranged in matrix and each of the memory cells has at least three storage states, a write circuit for writing data to the memory cells, first and second write verify means each constituted of a sense amplifier, a data latch circuit and a detection circuit, for verifying an insufficient-written state of a memory cell and an excess-written state of a memory cell, respectively, an additional write circuit for additionally writing data to the memory cell in the insufficient-written state, and an additional erase circuit for additionally erasing data from the memory cell in the excess-written state.

Abstract: A test vector system (157) and method for generating and verifying test vectors for testing integrated circuit speed paths involves accessing a circuit model (160), a list of circuit paths (162) and a test vector verifier (165). A single circuit path, referred to as a selected path, is selected from the paths (162). Once logical constraints are set, hazard-free logical values and logical values for both the second test clock cycle and the first test clock cycle are justified. Test vectors are generated in response to the justified values and the test vectors are used as input to the test vector verifier. The test verifier produces patterns that provide robust delay path fault tests for the given path. The test patterns are serially shifted and double-clocked in an integrated circuit or electrical circuit manufactured in accordance with circuit model (160) to determine time delay path faults.