Abstract: An amplitude modulated optical analog signal transmission system with an automatic calibration process is disclosed. The system provides accurate, continuous real-time signal transmission by using two or more optical transmission channels to carry the transmission signal, with the channels automatically synchronized and switched such that one channel carries the signal while the other channel is being calibrated. At least one of the channels is carrying the signal at any time, and the switching of the channels is performed such that them is no apparent perturbation of the signal caused by the calibration process. In the steady state the calibration process reduces the DC offset and gain errors of both optical transmission channels, making their individual responses accurate and substantially identical, so that the output of either channel alone or the average of their outputs, selected at the appropriate times, provide accurate representation of the transmission signal.

Abstract: A process for reducing the test requirements of memory devices once they are packaged into modules by using a unique identification of a memory device based on the locations or types and locations of some of the defects in that memory device. The unique identification is used as an index to access a database containing more information on the types and locations of defects within that memory device. The information is then stored in a non-volatile memory on the module containing that memory device.

Abstract: The memory control this invention includes a microprogram-read-only-memory (CROM) containing micro-instructions for operation of an integrated-circuit memory, a program counter multiplexer (PCM) to select instructions from the control-read-only-memory, a micro-instruction decoder with BILBO control (MID/BC), a test input multiplexer (TIM) to test control signals, an optional status output register (SOR) to generate control signals, and a subroutine stack (SS) to allow function calls. A program counter (PC) takes an index signal from the micro-instruction decoder with BILBO control (MID/BC) and a signal from the program counter multiplexer (PCM), and from those signal, generates a next microcode address. Complex program, erase, and compaction instructions for the integrated-circuit memory are implemented using a relatively small number of control-read-only-memory locations and using a relatively small surface area on the memory chip.

Abstract: A test pattern generating apparatus including circuit information/fault information input means 101, test pattern input generating means 102, test pattern input assigning means 103, logical simulation means 104, fault defining means 105, fault simulation means 106, fault extracting(detecting) means 107, initial test pattern extracting means 108, test pattern converting means 109 for assigning undefined values to an initial test pattern, final test pattern extracting means 110, test pattern generation judging means 111, all extracted test pattern merging means 112, and merged test pattern output means 413.

Abstract: A fail analysis device is to count the number of fails with respect to a memory under test detected during the test.

Abstract: A method and apparatus for analyzing a programmable logic device (PLD) that provides access to internal nodes of the circuit. The method and apparatus in accordance with the present invention uses a shadow programmable logic device to emulate the target PLD while coupling input and output terminals of the shadow PLD so as to provide more information about the target PLD than can be obtained from the target PLD itself. Also, the shadow PLD can implement internal stimulus and/or response functions to provide improve analyzing capability not possible with the target PLD alone.

Abstract: A boundary scan register allows for simplified testing of interconnections between integrated circuits. The interconnections between integrated circuits are characterized according to net type. Each net type has one or more mask registers that drive control inputs to each boundary scan register that drives a net of that type. One integrated circuit is configured to drive, while the others are configured to receive. The boundary scan registers are initialized to predetermined values, the mask registers are loaded, and clocks are pulsed to perform the needed tests. The results are then scanned out of the boundary scan registers, and a compression circuit compresses the test results data.

Abstract: A ROM repair circuit comprising a ROM cell array having a plurality of cells, each of the cells storing information inputted through a corresponding one of a plurality of bit lines under a control of data inputted through a corresponding one of a plurality of word lines, column and row address detectors for detecting column and row addresses corresponding to a failed one of the cells in the ROM cell array from addresses applied in a test mode and generating error detect signals in accordance with the detected results, respectively, and column and row address converters responsive to the error detect signals from the column and row address detectors to replace the column and row addresses corresponding to the failed one of the cells in the ROM cell array with different column and row addresses corresponding to a different one of the cells in the ROM cell array in which is stored the same information as normal information stored in the failed cell prior to the failure.

Abstract: An electronic integrated circuit includes a signal path connected between the functional logic (15) thereof and an external terminal thereof, which signal path includes a memory element (121, 123, 127). The memory element includes the buffer (11, 19, 21) that drives signals to/from the terminal.

Abstract: A method and apparatus for handling multiplexer contention during scan. During a test scan of a multiplexer circuit, it is possible for multiple inputs of a multiplexer to be selected at the same time in what is referred to as multiplexer contention. If the selected inputs are of different logical values, this contention may result in high power consumption and damage to the circuit. The invention prevents the adverse consequences of multiplexer contention by disabling one direction of the driving capability for each driving gate in the multiplexer during a scan. Thus, the multiplexer output can be driven to only one logical value regardless of the logical values of the selected inputs. A controllable impedance element, such as a transistor, is coupled between an input driving gate of a multiplexer circuit and a voltage supply node. The impedance element is responsive to a scan control signal, such that the impedance element is disabled, i.e., at high impedance, during a scan procedure.

Abstract: An electronic testing system can test an electronic device which has more signal pins or pads (i.e., contacts) than the maximum number of tester probes. The testing system connects the contacts to the tester such that groups of contacts share individual tester signal lines. The testing system uses special selector logic on the device to be tested to determine which particular contacts of the groups are "currently output active", or capable of transmitting data. At each step in the testing procedure, the system can vary the sets of contacts which are chosen to be currently output active, thereby resulting in a high percentage of the possible states of the device being tested.

Abstract: A scan cell design includes a bypass mode in which the scan input (SI) of the cell is connected directly to the scan output of the cell by a connection that bypasses the scan memory (M1) of the cell.

Abstract: A system and method for using standard JTAG protocol for testing protocol compliant and non-protocol compliant digital devices without altering the JTAG protocol or the non-compliant device. A specialized Test Access Port Controller controls and monitors the states applied to the non-compliant device in order to eliminate the PAUSE state in the non-compliant device and to limit the Run-Test/Idle state to one clock period.

Abstract: A plurality of different fault locating functions are provided in a communication system comprising a plurality of terminals connected to a data transmission channel. The functions are at different levels, respectively, ranging from a level for rapid fault location to a level for reliable and sure fault location. Upon detection of an occurrence of a fault, one fault locating function is performed. If the fault is not located accurately located, another fault locating function of a level for more reliable is performed, thus the functions are performed sequentially in the order from the level for rapid location to the level for more deliberate and reliable location. Preferably, the channel is reconfigured to avoid the fault, according to the fault located by the functions of the respective levels. With this arrangement, a fault which does most possibly occur can be located quickly, while another fault difficult to locate can be located accurately.

Abstract: Design rule check errors are outputted to a working file based on data entered from a mask pattern data storage unit and data entered from a design standard file, and a false error is removed from the design rule check errors based on data entered from the mask pattern data storage unit and data entered from the working file, and outputted as a design rule check result. The false error which is removed from the design rule check errors is determined based on whether the design fuel check errors overlap the mask pattern data stored in the mask pattern data storage unit.

Abstract: The present invention provides a test method of SOA (Single-Order Addressed) memory utilizing address data backgrounds applied to memory circuits. A memory test operation is performed using a total of (log.sub.2 N+1) address data backgrounds on an SOA memory having N mutually different addresses. Each address data background is written and read, then the inversion is written and read. Finally the address data background is again written and read for a total of 6 N(log.sub.2 N+1) operations.

Abstract: Input and output boundary scan cells respectively include latchable input and output buffers (103,40) which respectively utilize the input and output buffers of the integrated circuit in which the boundary scan cells are prodded. The latchable input and output buffers provide the input and output boundary scan cells with a low overhead latching function.

Abstract: A built-in self test architecture for testing one or more integrated circuits. Each circuit is provided with an interface compatible with IEEE standard 1149.1 and one or more scan registers containing scan cells for supplying input test data to, and receiving output test data from, the internal circuitry of the integrated circuits, a pseudo-random pattern generator for supplying patterns of test data to the boundary scan register, and a pattern compressor for compressing the output test data into a signature. The architecture also includes a single clock multiplexer, located external to the integrated circuits, for selectively supplying a system clock or a test clock to the testing components of each integrated circuit.

Abstract: In a disc drive storage system employing a track level redundancy sector for reconstructing a data sector unrecoverable at the sector level, the latency of the storage system is minimized by performing a write operation according to the following steps:1. seek to the target track corresponding to the sector(s) to be written;2. once at the target track, wait for the recording head to reach the first sector in the track (sector 0);3. begin reading and processing the sectors in the target track to regenerate the redundancy sector;4. when the recording head reaches the target sector(s), combine the new data sector(s) with the regenerated redundancy sector, switch to a write operation, and write the new sectors to the track;5. after writing the new data sectors to the track, switch back to a read operation and continue reading the data sectors in the track and combining them with the regenerated redundancy sector; and6.

Abstract: A data storage array is provided having a number, n, of sequential data storage areas for the storage of data. A valid status array including n bits is provided where there is a one to one correspondence between the bits of the valid status array and the data storage areas of the data storage array. When valid data are written into a data storage area, the status bit of the valid status array corresponding to this data storage area is set to indicate that valid data are present. When data are read out of the data storage area, the corresponding status bit is cleared indicating the absence of valid data. If the data storage array is one that is written to in a random access manner and read from sequentially, as a queue, then the valid status array would indicate the presence of valid data at the head of the queue for the data storage array.