Abstract: A transfer memory backup system for a RAID level 5 disk array storage system which includes a transfer buffer, wherein write data received by the array is written into a transfer buffer, and a write complete status signal generated, prior to the write data being written to the disk drives within the array. The transfer memory backup system includes a low power, industry standard PCMCIA (Personal Computer Memory Card International Association) device along with a small, temporary voltage source made up of a small rechargeable battery or a high capacitance gold capacitor. Upon the detection of a disk array storage system failure, low power logic provides continuous refresh for the transfer buffer as well as power to the components included in the transfer memory backup system upon a disk array storage system failure. A low power CMOS microprocessor with self contained microcode (mask programmable ROM) controls the transfer of data from the transfer buffer to removable storage medium within the PCMCIA device.

Abstract: A highly reliable online system is disclosed which is provided with a backup computer center (sub-online system) in addition with an original computer center (main online system) in order to improve the reliability of the online system. With respect to the database, the main online system is provided with an original database (main database) while the sub-online system is provided with a backup database (sub-database) which is a duplicate of the main database. The main online system and the sub-online system are connected through a transmission path. Information on an update performed in the main database is transferred to the sub-online system through the transmission path to thereby update the sub-database in a manner similar to the main database. Terminal units are normally connected to the main online system, wherein the main database is updated by transactions inputted from the terminals.

Abstract: A half-latch for a scan latch is described. The half-latch has an input terminal for receiving an input signal a first control terminal for receiving a clock signal and an output terminal. When enabled, the half-latch adopts a data transfer state in which it transmits a signal from its input terminal to its output terminal. Alternatively, the half-latch can adopt a data holding state in which a signal is stored on the output terminal, these states being selected in dependence on the state of the clock signal. The half-latch described herein has a second control terminal which receives the control signal to selectively disable the half-latch. This allows a common clock signal to be used when a scan latch is constructed using these half-latches.

Abstract: A block code decoding method finds the highest path metric path in a forward direction of a trellis diagram from an initial state of the trellis diagram to a final state. Next, the highest path metric path is found in a backward direction from the final state back to the initial state. The metrics of these two highest path metric paths are compared and the path having the absolute highest metric, in either direction, is chosen as a most likely path through the trellis diagram.

Abstract: The present invention relates to a fail-safe control interface including branches for providing signals having a safe state or a non-safe state. Each branch comprises inputs for receiving at least two binary control signals (Si, Si*); a source of a non-safe state (Fe) connectable through a basic chain of elements (14, 15) to an output (Oi) when the control signals realize a predetermined combination; a concurrent checker (17) providing an error detection signal (g1, g2) if the inputs of a pair of its inputs are at predetermined states; and means (14*) for providing a first input of said pair of inputs with a signal corresponding to the state of said output and the second input of said pair of inputs with a signal corresponding to the output of a duplicate chain of the basic chain, this duplicate chain reacting like the basic chain in response to the control signals.

Abstract: Automatic parametric testing of a system can be achieved by varying a parameter such as speed, voltage, and/or temperature, and then monitoring system performance. Such testing can be used to determine whether a given system meets specifications and performance variations from system to system.

Abstract: A DFT technique for the detection of bridging faults in CMOS and BiCMOS logic ICs, employs purposely integrated monitoring inverters, driven by signal nodes of the functional circuits to be tested, for revealing the presence of intermediate voltages of a critical value. The monitoring inverters are supplied through a dedicated shadow line that is connected to either one of the supply rails of the functional circuits through a load: a resistance, for a static implementation, or a capacitor, for a dynamic (clocked) implementation. Absence of series connected built-in current sensors (BICSs) avoids degradation of the performance of the functional circuits and is compatible with scaling down of the power supply and with on-line testing techniques. Only critical bridging faults may be reliably and selectively detected, thus reducing the number of rejects, failing a conventional IDDQ test.

Abstract: An integrated circuit (IC) device implemented according to an architectural design that specifies that the IC device is required to have one functional module, to perform a first function, connected to another functional module, to perform a second function. The IC device includes a first IC chip having a plurality of first functional modules implemented thereon. Some of the first functional modules are defective and others of the first functional modules are non-defective. At least one of the non-defective first functional modules is operable to perform the first function. The IC device also includes a second IC chip having a plurality of second functional modules implemented thereon. Some of the second functional modules are defective and others of the second functional modules are non-defective. At least one of the non-defective second functional modules is operable to perform the second function.

Abstract: A logic circuit and a technique for repairing faulty memory cells internally by employing on-chip testing and repairing circuits in an ASIC system. The test circuit detects column line faults, row faults, and data retention faults in a memory array. The repair circuit redirects the original address locations of the faulty memory lines to the mapped address locations of the redundant column or row lines. This repair scheme includes redundant column lines attached to each of the I/O arrays in the memory array and redundant row lines to replace detected memory faults. These testing and repairing procedures are performed within the chip without the aid of any external equipment.

Abstract: Circuitry for reconfiguring a pin of an integrated circuit. The reconfiguration circuitry includes a multiplexer, whose output is coupled to the pin. Upon powering-up the integrated circuit, the multiplexer couples to the pin to a first signal that conforms to the historical definition of the pin's function. The user reconfigures the pin by issuing a command that causes the multiplexer to couple a second signal to the pin. This second signal behaves in a manner more useful to the user. The switch from the first signal to the second is achieved via a reconfiguration register, which generates the multiplexer's select signal. A control engine within the integrated circuit responds to the reconfiguration command by writing once to the reconfiguration register. The pin remains reconfigured until the integrated device is powered down.

Abstract: Apparatus and method that incorporate bussed test access port interface into a system control interface for testing and controlling system logic boards in a manner that is fully compliant with the IEEE 1149.1 standard, while conserving system controller card signals. The apparatus incorporates six signals per interface, which includes the five standard signals as defined by IEEE 1149.1 standard plus a maintenance enable (ME) signal. Four of the standard signals, TCK, TMS, TDI and TRST* are bussed among multiple system logic boards, while the ME signals and the TDO signals are connected in a point-to-point manner between the system controller card and system logic boards. Instruction and data on the TCK, TMS, TDI, and TRST* signals are simultaneously bussed to all system logic boards. These four signals are received by each system logic board through an interface enable circuit, controlled by the ME signal line.

Abstract: A test pattern generator accompanying digital integrated circuits for successively generating a plurality of test patterns for a built-in self test. A plurality of shift registers are serially connected in a loop for successively outputting the test patterns in response to a clock signal. At least one logic gate is connected among the shift registers. At least one control means is connected within the loop. Using such a configuration, the shift registers are set to an initial pattern. The shift registers are then set to one of a plurality of test patterns. The test patterns are then successively output through the shift registers in response to the clock signal.

Abstract: A test-vector generating system (200) controls a processor (110) having a paradigm floating point functional unit (160) which executes a paradigm floating point instruction set. The system includes computer program modules including an interactive test selection process (202) in which a test instruction is selected from the paradigm instruction set, an operand data generation process (222), a test instruction execution process (226) in which the paradigm functional unit executes the test instruction operating upon the generated operand data and a test vector result recording process (208) in which a test vector result of the test instruction execution is recorded.

Abstract: A data erasing device erasing designated data includes designating circuitry for designating one of two groups in a storage medium. The two groups comprise a first group including an upper block preceding a designated block, and a second group including a lower block following the designated block. Erasing circuitry is provided for erasing data recorded in blocks which are included in the designated group. Preferably, a designated block is one track in a recording disk, and the tracks above and/or below the designated track are erased.

Abstract: An IEEE Std. 1149.1 boundary scan circuit which is capable of performing built-in self-testing includes a logic circuit, cascaded input boundary-scan cells that form an input boundary-scan register connected to input nodes of the logic circuit, cascaded output boundary-scan cells that form an output boundary-scan register connected to output nodes of the logic circuit, and a test access port system for controlling operation of the input and output boundary-scan cells. The test access port system provides a built-in self-test control signal to the input and output boundary-scan cells when executing built-in self-testing. The input boundary-scan register is reconfigurable to operate as a test pattern generator that provides test patterns to the logic circuit for a predetermined number of clock cycles upon receipt of the built-in self-test control signal.

Abstract: An audio data processing system (10) is described which comprises a control processor (12) coupled to an execution controller (22) through a bus (21). The control processor (12) serves as a master processor to control the operation of the execution controller (22) which in turn controls the operation of a multiplier accumulator (28). An ancillary data handler (20) is provided to retrieve ancillary data from an input FIFO buffer (18). Audio data is retrieved from the input FIFO buffer (18) by the control processor (12) and processed audio data is output through an output block (30).

Abstract: A test control device for controlling the distribution of test data is connectable in parallel to a plurality of integrated circuits.

Abstract: Apparatus for controlling a length of a period during which the output circuitry of a memory array waits before latching the output data including apparatus for detecting the presence of an error in data read from an memory array, apparatus for providing a first value to determine a wait period, apparatus responsive to the detection of an error for providing a second value, apparatus responsive to the first value for generating a signal to latch a data output from the memory array after a first period and responsive to the second value for generating a signal to latch a data output from the memory array after a second period.

Abstract: Automatic test equipment with a programmable timing generator. In the timing generator, the required delay is split into a course delay, a frequency adjustment delay, and a fine delay. The fine delays for successive cycles are temporarily stored. As the course delays pass, the fine delays are retrieved and used to generate edge signals. The frequency adjustment delay is used to offset the time at which the fine delay is retrieved by a fraction of a the resolution of the course delay. This arrangement allows the fine delay values to be retrieved at a higher rate than the rate at which the signals representing the required delays were generated. With this arrangement, the edges can be generated in a high frequency burst mode even though much of the timing generator is implemented with circuitry that has a lower operating frequency. A significant cost savings results by providing high frequency operation with less expensive components of lower operating frequency.

Abstract: A method and an apparatus for recording and reproducing information for use with an optical disk apparatus in which a pit edge recording method is used. According to the pit edge recording method, the leading edge and the trailing edge of a hole pit or a record domain generated during a recording operation are dealt with as information. During the recording, the recording pulse width and the recording power are corrected, and during the reproduction, the variation in the edge position is corrected.