Patents Examined by Vincent T Tran
  • Patent number: 8250386
    Abstract: A processor circuit having reduced power consumption includes an analog front end operative to receive an analog signal supplied to the processor circuit and to generate a digital signal indicative of the analog signal. The processor further includes a digital back end operative to generate a digital output signal as a function of the digital signal generated by the analog front end. A buffer is coupled between the analog front end and the digital back end. In a first mode of operation, the digital back end operates at a substantially same data rate as the analog front end and the buffer is bypassed. In a second mode of operation, the digital back end operates at a higher data rate than the analog front end and the buffer is used to store outputs of the analog front end.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: August 21, 2012
    Assignee: Agere Systems Inc.
    Inventor: Nils Graef
  • Patent number: 8140840
    Abstract: Embodiments of the present invention provide a method, system and computer program product for a low power document editing mode for mobile computing devices. In an embodiment of the invention, a battery powered computing device can be configured for power optimized document editing, the computing device. The device can include a central processing unit (CPU), both coupled to a battery, memory, fixed storage and a display within a single computing case. The device also can include a primary personal computing operating system and also an auxiliary low-power consumption operating system each stored in fixed storage, each including a configuration to access an editable document in the fixed storage. Finally, the device can include a boot read only memory (ROM) programmed to selectively bootstrap into either the primary personal computing operating system or the auxiliary low-power consumption operating system.
    Type: Grant
    Filed: April 18, 2008
    Date of Patent: March 20, 2012
    Assignee: International Business Machines Corporation
    Inventors: Kulvir S. Bhogal, Gregory J. Boss, Rick A. Hamilton, II, Robert R. Peterson
  • Patent number: 8078856
    Abstract: Systems, methods, and computer-readable media provide for notification of power-on self-test (POST) data using an output device that is externally connected to a target computer system undergoing the POST via a data cable. Embodiments include a data transport module having an interface for receiving POST data from a debug module within the firmware of the target computer system and a notification application executed on the output device. The POST data transport module receives POST data and writes it to one or more hardware registers associated with an external port of the target computer system. The POST data is transferred to the data cable from the hardware registers and is received from the cable by the notification application of the output device. The notification application generates a notification corresponding to the received POST data and displays the notification on a display of the output device.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: December 13, 2011
    Assignee: American Megatrends, Inc.
    Inventors: Stefano Righi, Ashraf Javeed
  • Patent number: 8069357
    Abstract: A multi-processor control device according to an example of the invention comprises a cooperative control unit which determines priorities of requests issued from processors to a shared resource which are used to suppress a total power consumption of the processors within a range in which performance constraints of programs executed by the processors are satisfied, and determines a frequency of each of the processors so as to suppress the total power consumption within the range in which the performance constraint of the each program is satisfied, a first control unit which issues requests from the processors to the shared resource in accordance with priorities determined by the cooperative control unit, and a second control unit which controls the frequency of each of the processors in accordance with the frequency determined by the cooperative control unit.
    Type: Grant
    Filed: May 16, 2008
    Date of Patent: November 29, 2011
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Hiroshi Nakamura, Masaaki Kondo, Takashi Nanya, Ryo Watanabe
  • Patent number: 8032778
    Abstract: Apparatus, systems, and methods are disclosed that operate to adjust power received by a clock distribution network at least partially based on operating conditions of an integrated circuit. Additional apparatus, systems, and methods are disclosed.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: October 4, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Feng Lin
  • Patent number: 8020021
    Abstract: Method of controlling a wind power system comprising a plurality of system elements, the wind power system including a plurality of data processors distributed in the system elements, the method includes the steps of: synchronizing at least a part of the data processors to at least one reference signal distributed to the data processors from a time synchronization arrangement, associating the data processors with local clock generation circuitries, wherein the local clock generation circuitries associated with data processors of a first subset of the data processors have a peak-to-peak tracking jitter higher than or equal to a predetermined threshold value and wherein a second subset of the data processors have a peak-to-peak tracking jitter less than the predetermined threshold value, controlling at least one of said system elements at least partly by mechanism of a data processor from said first or second subset of data processors.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: September 13, 2011
    Assignee: Vestas Wind Systems A/S
    Inventor: John Bengtson
  • Patent number: 8020023
    Abstract: Exemplary systems and methods include a distribution device that maintains a clock rate and distributes a series of tasks to a group of execution devices. Each task has a plurality of samples per frame associated with a time stamp indicating when the task is to be executed. The execution devices execute the series of tasks at the times indicated and adjust the number of samples per frame in relation to the clock rate maintained by the distribution device.
    Type: Grant
    Filed: May 9, 2007
    Date of Patent: September 13, 2011
    Assignee: Sonos, Inc.
    Inventors: Nicholas A. J. Millington, Michael Ericson
  • Patent number: 8020016
    Abstract: To reduce the electric power consumption in a computer system having at least one server and at least one data processing apparatus, the data processing apparatus includes an electric power consumption state control module by which electric power consumption of the data processing apparatus can be changed, obtains a use relationship between each server and each processing apparatus included in the computer system, monitors a change in a state of the server, searches for a related data processing apparatus in the use relationship with the server, obtains a state of at least one related server in the use relationship with the related data processing apparatus, determines whether an electric power consumption state of the related data processing apparatus is to be changed or not based on the state of the related server, and changes the electric power consumption state of the related data processing apparatus.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: September 13, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Keisuke Hatasaki, Yoshifumi Takamoto, Akira Fujibayashi
  • Patent number: 8019984
    Abstract: A method for controlling an autostart of a data application and a video playback apparatus thereof are provided. The method for controlling an autostart of a data application includes determining stored setup information of a start procedure of the data application, and executing the data application according to the determined setup information of the start method of the data application. Therefore, it is possible to prevent the data application from being automatically started unintentionally, and only the required data application can be automatically started by user control, and accordingly, user convenience is enhanced.
    Type: Grant
    Filed: April 6, 2007
    Date of Patent: September 13, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Moon-Soo Kim
  • Patent number: 8020027
    Abstract: The tension between fmax and Tco in a specialized processing block of a programmable integrated circuit device can be reduced by providing variable delays on the clock inputs of the pipeline registers within the specialized processing block. This allows the introduction of beneficial skew that allows slower functions to be performed within the specialized processing block rather than outside the block, thereby reducing Tco, without slowing down the clock—i.e., without reducing fmax. This technique may also apply to other specialized blocks such as memory.
    Type: Grant
    Filed: March 17, 2008
    Date of Patent: September 13, 2011
    Assignee: Altera Corporation
    Inventor: Michael D. Hutton
  • Patent number: 8015420
    Abstract: A system and method for power management of storage enclosures are disclosed. A system may include a storage enclosure and a host communicatively coupled to the storage enclosure. The storage enclosure may include at least one storage resource and a management module. The host may be configured to: (a) communicate data to the at least one storage resource via a particular transmission protocol; (b) communicate a power down command via the particular transmission protocol to the storage enclosure, the power down command operable to transition the storage enclosure from a high-power state to a low-power state; and (c) communicate a power up command via the particular transmission protocol to the storage enclosure, the power up command operable to transition the storage enclosure from the low-power state to the high-power state.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: September 6, 2011
    Assignee: Dell Products L.P.
    Inventors: Jacob Cherian, William Lynn
  • Patent number: 8015424
    Abstract: The present invention relates to a portable information apparatus which can realize electrical power for a longer period of time. Under the condition that the suspending mode is set, when an exclusive key is manipulated, a switch monitoring circuit detects this condition and issues an interruption to the CPU. In this timing, the CPU supplies the necessary electrical power to the CD-ROM controller, CD-ROM drive and audio circuit which are required for reproduction of CD. Thereby, a CD can be reproduced under the suspending mode.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: September 6, 2011
    Assignee: Sony Corporation
    Inventor: Yasuhiko Sakagami
  • Patent number: 8010777
    Abstract: Embodiments are provided to deploy a number of computing devices based in part on a deployment file, but the embodiments are not so limited. In an embodiment, a dispatch application can be used to deploy a number of computing devices, wherein the deployment includes a number deployment parameters and functions associated with a configuration of the number of computing devices. The dispatch application can be used to deploy a number of computing devices, including virtual devices, logical devices, and other devices and systems. Other embodiments are available.
    Type: Grant
    Filed: July 2, 2007
    Date of Patent: August 30, 2011
    Assignee: Microsoft Corporation
    Inventors: Durgesh Nandan, Shuyi Hu
  • Patent number: 8010813
    Abstract: Disclosed is a design structure for an associated first system for extending product life of a second system in the presence of phenomena that cause the exhibition of both performance degradation and recovery properties within system devices. The first system includes duplicate devices incorporated into the second system (e.g., on a shared bus). These duplicate devices are adapted to independently perform the same function within that second system. Reference signal generators, a reference signal comparator, a power controller and a state machine, working in combination, can be adapted to seamlessly switch performance of that same function within the second system between the duplicate devices based on a measurement of performance degradation to allow for device recovery. A predetermined policy accessible by the state machine dictates when and whether or not to initiate a switch.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: August 30, 2011
    Assignee: International Business Machines Corporation
    Inventors: Kenneth J. Goodnow, Stephen G. Shuma, Oscar C. Strohacker, Mark S. Styduhar, Peter A. Twombly, Andrew S. Wienick, Paul S. Zuchowski
  • Patent number: 7996705
    Abstract: A multilevel input interface device connected to a signal bus including one or more data lines that transmit an M-level signal and a clock line that transmits a transmission clock signal indicating the timings of reading level information for the M-level signal, includes: a threshold value generation unit that produces a plurality of voltage outputs as a plurality of variable comparison reference signals according to the level-varying supply voltage; a level detection unit that compares, in synchronization with the transmission clock signal, the M-value level signal with the variable comparison reference signals and generates a logic output corresponding to an instantaneous value of the M-level signal; and a logic circuit unit that converts the logic output to a data signal.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: August 9, 2011
    Assignee: Seiko Epson Corporation
    Inventor: Kesatoshi Takeuchi
  • Patent number: 7991990
    Abstract: A memory access system for accessing a basic input output system (BIOS) program is provided. The memory access system includes a flash memory, a CPU, a peripheral component interconnect (PCI) slave, an address converter and a flash memory controller. The flash memory stores a number of BIOS data of the BIOS program, and each BIOS data corresponds to a default BIOS address and is allocated in a flash memory type BIOS address. The CPU delivers a BIOS access instruction. The BIOS access instruction corresponds to a default target address of the default BIOS addresses. After the PCI slave interprets the BIOS access instruction, the address converter converts the default target address into a flash memory type target address, which is one of the flash memory type BIOS address. The flash memory controller accesses the BIOS data allocated at the flash memory type target address accordingly.
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: August 2, 2011
    Assignee: VIA Technologies, Inc.
    Inventors: Chien-Ping Chung, Lin-Hung Chen
  • Patent number: 7991992
    Abstract: Disclosed herein are SOC devices with peripheral units having power management logic.
    Type: Grant
    Filed: March 13, 2007
    Date of Patent: August 2, 2011
    Assignee: Intel Corporation
    Inventors: Teck Ee Guan, Kai Hoong Fong
  • Patent number: 7992012
    Abstract: In order to make it possible to reduce the time required for the central power source control unit to perform power source control of the power source unit of the expanded apparatus, the central power source control unit includes: a power source control information holding unit which holds power source control information written by a central processing circuit for performing power source controlling of another power source device; and a transmission control unit which transmits the power source control information held in the power source control information holding unit to another power source control circuit that performs power source control of said another power source device.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: August 2, 2011
    Assignee: Fujitsu Limited
    Inventor: Tetsuya Kaizu
  • Patent number: 7987351
    Abstract: A secondary boot code may be copied to memory during execution of a primary boot code, and executing the copied secondary boot code after completion of execution of said primary boot code. Access to the primary and said secondary boot code may be restricted during execution of the primary boot code and the copied secondary boot code. The copied secondary boot code may be verified after the secondary boot code is copied to the memory. Access to the primary boot code may be blocked or barred during execution of the copied secondary boot code. Access to the secondary boot code may also be blocked or barred after completion of execution of the copied secondary boot code. The memory may comprise double-data-rate synchronous dynamic random access memory (DDR). The primary and/or the secondary boot code may reside or be stored in FLASH memory.
    Type: Grant
    Filed: May 10, 2007
    Date of Patent: July 26, 2011
    Assignee: Broadcom Corporation
    Inventor: Andrew Dellow
  • Patent number: 7987348
    Abstract: In some embodiments, the invention involves speeding boot up of a platform by initializing the video card early on in the boot process. In an embodiment, processor cache memory is to be used as cache as RAM (CAR). Video graphics adapter (VGA) card initialization uses the CAR instead of system RAM to perform initialization. A portion of the firmware code, interrupt vector tables and handlers are mirrored in the CAR, from flash memory to mimic the behavior of system RAM during the video initialization. VGA initialization may occur before system RAM has initialized to enable early visual feedback to a user. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 30, 2007
    Date of Patent: July 26, 2011
    Assignee: Intel Corporation
    Inventors: Robert C. Swanson, Michael A. Rothman, Mallik Bulusu, Vincent J. Zimmer