Abstract: A maximum power usage setting for a computing device is based on one or more of: a user-specified setting corresponding to how often a frequency of a processor of the computing device is likely to have to be decreased to reduce power usage by the computing device; an average frequency of the processor during a previous period in which the computing device was operated; a minimum frequency of the processor during the previous period; a maximum power that the computing device used during the previous period; and, a nominal frequency of the processor. When the computing device starts to use more power than the maximum power usage setting, the power used by the computing device is reduced so as not to exceed the setting, such as by decreasing the frequency at which the processor operates.

Abstract: A method for power management of a CPU and a system thereof, which drive the CPU to enter a more efficient power saving state are disclosed. A chip of the present invention sends a first control signal to drive the CPU to wake from a non-snooping sleep state and enter a normally executing instruction state as well as a system management mode to execute a system management interrupt routine. Then the chip enables an arbiter to transmit a bus master request to the CPU for processing. After completing the processing of the bus master request, the chip disables the arbiter and the CPU drives the chip to send a second control signal to drive the CPU to return to the non-snooping sleep state according the system management interrupt routine.

Abstract: A system and method adjusts the polarity of power provided over Ethernet cabling according to configuration information received.

Abstract: Solid state power controllers are described that include a switch controlled by a microcontroller and communication contacts. In one aspect of the invention, the microcontroller is galvanically isolated from the communication contacts using magnetoresistive isolation. In another aspect of the invention a number of solid state power controllers are connected to an external microcontroller to form a power distribution array. In addition, messages exchanged between the external microcontroller and the solid state power controllers can be used to configure the solid state power controllers and provide a user interface.

Abstract: An information processing apparatus that has multiple functional parts and power management domains that serve as control units when supplying power to the functional parts, and that autonomously controls supply of power to the power management domains, the apparatus including a power supply control part that supplies power to only a power management domain that includes the functional part associated with execution of an input instruction, and that stops the power supply to the power management domain in response to termination of execution of an instruction by the functional part; and an execution result storage part that stores a result generated by execution of an instruction by the power management domain to which power is supplied by the power supply control part, independently of the power supply control part supplying power and stopping the supply of power; wherein, after supply of power to a power management domain that terminates execution of an instruction is stopped by the power supply control par

Abstract: A system and method to enable teamed network environments during network based initialization sequences is disclosed. In one form of the disclosure, an information handling system can include a plurality of communication modules. One of the communication modules can be used to store a first teaming application. The information handling system can also include a processor configured to execute the first teaming application to provide a teamed network environment using the plurality of communication modules to load an operating system during a pre-boot initialization.

Abstract: A communication apparatus is provided. The communication apparatus includes a transmission unit adapted to transmit data via a network, a receiving unit adapted to receive data supplied via the network, an interface unit adapted to supply to-be-transmitted data to the transmission unit and extract particular information from data received by the receiving unit, and a control unit configured to control an operation state of the interface unit.

Abstract: Provided is a system including a computer, a display device for performing display based on a signal from the computer, and an access point for performing communication between a wired network and a wireless network and disposed between the computer and the display device. In response to operation for turning ON the display device or to a power ON instruction from another client device, the access point is activated and sends an activation signal for activating the computer. Upon receiving the activation signal, the computer is activated and outputs a signal to the display device. Further, in response to operation for turning OFF the display device or to a power OFF instruction from another client device, the access point sends a power shutoff signal to the computer and shuts off its own power. Upon detecting the power shutoff signal, the computer performs a shutdown process. When the signal from the computer stops being received, the display device shuts off its own power.

Abstract: A system and method of controlling power consumption are provided. The example method may be directed to controlling power consumption in a system including first and second interface blocks, and may include transitioning a first interface block to a power saving mode in response to a status of a first transmission channel, the first transmission channel configured to forward information from the first interface block to a second interface block and transitioning a second interface block to the power saving mode in response to a status of a second transmission channel, the second transmission channel configured to forward information from the second interface block to the first interface block.

Abstract: A method is described that involves storing active sleep mode software instructions to be executed by a low end central processing unit into an on chip cache of a high end central processing unit that caches normal active mode software instructions executed by the high end central processing unit. The active sleep mode software instructions are to be executed by the low end central processing unit during an active sleep mode. The normal active mode software instructions are executed by the high end central processing unit during a normal active mode. The active sleep mode consumes less power than the normal active mode.

Abstract: An information processing apparatus has a multi-valued NAND nonvolatile memory including a plurality of word lines and a plurality of memory cells connected to the respective word lines. Each memory cell has a plurality of threshold voltages, and is divided into a first and a second storage area. A program code is stored in the first storage area, and user data is stored in the second storage area. The apparatus also includes a volatile memory to which the program code is transferred from the multi-valued NAND nonvolatile memory. The apparatus further includes a CPU connected to the volatile memory and configured to operate based on the program code transferred to the volatile memory.

Abstract: A remote monitor module for power initialization of a computer system includes a monitor logic and a BMC (Baseboard Management Controller). The monitor logic is in circuit connection with a power-up sequence controller and several basic voltage domains on a system board of the computer system. The monitor logic also defines a monitor power-up sequence to perform a basic power-up sequence defined in the power-up sequence controller and allow system changes in power initialization. Extra voltage domain(s) may be enabled and monitored according to the monitor power-up sequence. Eventually, multiple power initialization event/state signals are transmitted by the monitor logic to a remote management host through the BMC.

Abstract: Methods and apparatus for delaying a clock signal for a multiple-data-rate interface. An apparatus provides an integrated circuit including a frequency divider configured to receive a first clock signal and a first variable-delay block configured to receive an output from the frequency divider. Also included is a phase detector configured to receive the first clock signal and an output from the first variable-delay block, and an up/down counter configured to receive an output from the phase detector. A second variable-delay block is configured to receive a second clock signal and a plurality of flip-flops are configured to receive an output from the second variable-delay block. The first variable-delay block and the second variable-delay block are configured to receive an output from the up/down counter.

Abstract: Systems and methods for I/O fencing in a shared storage environment are provided. Prior to initiating an I/O request, when feasible, the current time from a local timer is compared to the current state of an interval obtained for the target device. As a result, a device reset occurring while the interval is viable does not arbitrarily end a multiphase I/O operation. However, a device reset occurring once the lease has expired results in a delay or termination of the multiphase I/O operation. As a result, multiphase I/O operations from initiating hosts that have lost contact with the shared storage environment are not allowed to corrupt the shared storage devices.

Abstract: An apparatus being connectable as a latch stage into a asynchronous latch chain comprises a reception interface, wherein upon receipt of the first signal at the reception interface, the apparatus switches to one of the first power saving mode and a second power saving mode, depending on the second signal at the reception interface and wherein the apparatus offers a first power consumption and a first wake-up time in the first power saving mode, and a second power consumption and a second wake-up time in the second power saving mode.

Abstract: A computer system with a main memory is equipped with an HDD that has a disk and a driving motor driving the disk, a non-volatile storage unit provided in the HDD storing therein a booting program of an operating system, and a control unit reading out the booting program stored in the non-volatile storage unit and loading the booting program onto the main memory before the driving motor reaches a normal speed as power is supplied to the computer system. With this configuration, there is provided a computer system capable of reducing the booting time of the HDD.

Abstract: During unexpected application shutdowns, application settings states are captured, and displayed application states are restored upon subsequent application restart. User data displayed prior to shutdown may also be restored to pre-shutdown states. Data representing in-use application settings states and in-use user data are stored on a periodic basis, or upon notification of an impending application shutdown. Upon restart, any application deployed prior to shutdown is re-deployed according to the stored application settings states for each application, and any in-use documents or other data may be re-deployed according to the stored user data.

Abstract: A circuit for deterministic unparking of a strand of a microprocessor having multiple clock domains is described. The circuit includes a first flip-flop and a second flip-flop. Each flip-flop has a data input connected to receive a respective unpark signal, a clock signal at respective clock frequencies, and a respective enable signal. Each enable signal is generated by a respective logic block, each including a counter and each operating at a respective one of the clock frequencies. The second flip-flop has a data input connected to an output of the first flip-flop, and outputs an unpark signal that is used to unpark a strand of the microprocessor in a deterministic manner.

Abstract: The present invention provides a computer system with a chronology generator for generating a chronology for a series of computer configurations.

Abstract: Methods and apparatuses provide voltage regulation for a processor. Control or configuration parameters for a voltage regulator (VR) are provided digitally over a configuration bus to a VR controller. The parameters may be provided directly from a storage element, or via a processing element or processor core. Based in whole or in part on the parameters, the VR controller provides an output control signal to affect a power output from a power converter to the processing element. In one embodiment, the VR controller is integrated onto the same IC as the processing element.