Abstract: A semiconductor detector device comprises a layer of semiconductor material for generating charge in response to an input event and an array of pixels for collecting charge. Tracks are connected to the pixels to supply signals representing the collected charge to a reader circuit. The pixels are grouped into sets, all the pixels within a set being connected to the same track, the sets of pixels being interwoven so that so that any group of n adjacent pixels capable of collecting charge generated by a single input event is connected to a combination of n tracks that is unique to the group of pixels, where n has a value of one of 2, 3 or 4. This allows detection of position of the area of charge collection on the basis of temporally coincident signals on a combination of at least n tracks.

Abstract: An object is at least one of a longer data retention period of a memory circuit, a reduction in power consumption, a smaller circuit area, and an increase in the number of times written data can be read to one data writing operation. The memory circuit has a first field-effect transistor, a second field-effect transistor, and a rectifier element including a pair of current terminals. A data signal is input to one of a source and a drain of the first field-effect transistor. A gate of the second field-effect transistor is electrically connected to the other of the source and the drain of the first field-effect transistor. One of the pair of current terminals of the rectifier element is electrically connected to a source or a drain of the second field-effect transistor.

Abstract: A method of gaming comprising: receiving an input indicative that a player accepts deferred payment in respect of at least one award awardable during play of a game; conducting the play to determine whether the at least one award is made; and providing an entitlement to the player to enable the player to obtain the award after a deferment period when the award is made to the player.

Abstract: An electronic system without using solder balls between electrical components, and without using interposer between chips and package substrate, without using a discrete system board for the chip package to mount. A chip is wrapped by molding material, a first redistribution circuitry is built on a bottom side of the molding material; a second redistribution circuitry is built on a bottom side of the first redistribution circuitry. A third redistribution circuitry is built on a bottom side of the second redistribution circuitry. Plated metal vias are configured between each two of the electrical components.

Abstract: An organic light-emitting display device includes a first substrate having transmitting regions and pixel regions separated from each other by the transmitting regions, a plurality of thin film transistors on the first substrate in the pixel regions, a passivation layer covering the plurality of thin film transistors, a plurality of pixel electrodes on the passivation layer and electrically connected to the thin film transistors, the pixel electrodes being in the pixel regions and overlapping the thin film transistors, an opposite electrode in the transmitting regions and the pixel regions, the opposite electrode facing the plurality of pixel electrodes and being configured to transmit light, an organic emission layer interposed between the pixel electrodes and the opposite electrode, and a color filter in corresponding pixel regions.

Abstract: An integrated circuit that includes: providing a substrate including a support structure, a dielectric layer, and a variable thickness film processed to include the dielectric layer within a recess of the variable thickness film; forming a gate over the variable thickness film; and forming a channel and a source/drain within the variable thickness film.

Abstract: A method of fabricating a microelectronic unit includes providing a semiconductor element having a front surface and a rear surface remote from the front surface, forming at least one first opening extending from the rear surface partially through the semiconductor element towards the front surface by directing a jet of fine abrasive particles towards the semiconductor element, and forming at least one conductive contact and at least one conductive interconnect coupled thereto. The semiconductor element can include a plurality of active semiconductor devices therein. The semiconductor element can include a plurality of conductive pads exposed at the front surface. Each conductive interconnect can extend within one or more of the first openings and can be coupled directly or indirectly to at least one of the conductive pads. Each of the conductive contacts can be exposed at the rear surface of the semiconductor element for electrical connection to an external device.

Abstract: A semiconductor device, comprising a first semiconductor portion having a first end, a second end, and a slit portion, wherein the width of the slit portion is less than the width of at least one of the first end and the second end; a second portion that is a different material than the first semiconductor portion, a third portion that is a different material than the first semiconductor portion, wherein the second and third portions are on opposite sides of the slit portion, and at least three terminals selected from a group consisting of a first terminal connected to the first end, a second terminal connected to the second end, a third terminal connected to the second portion, and a fourth terminal connected to the third portion.

Abstract: The display device includes a substrate, a thin film transistor (TFT), which includes a gate electrode, a semiconductor layer, and source and drain electrodes, on the substrate member, a passivation layer on the TFT and having an opening to expose a portion of the drain electrode, and a pixel electrode directly on the drain electrode and only within the opening.

Abstract: A semiconductor device includes a source finger electrode coupled to a source region in a semiconductor die, a drain finger electrode coupled to a drain region in the semiconductor die, where the source finger electrode includes at least one isolated segment and a main segment having a first portion and a second portion narrower than the first portion, whereby the source finger electrode reduces a drain-to-source capacitance of the semiconductor device. A common source rail is electrically coupled to the at least one isolated segment and the main segment of the source finger electrode. The drain finger electrode includes at least one isolated segment and a main segment having a first portion and a second portion narrower than the first portion. A common drain rail is electrically coupled to the at least one isolated segment and the main segment of the drain finger electrode.

Abstract: A method is described which includes providing a substrate and forming a first spacer material layer abutting a gate structure on the substrate. A second spacer material layer is formed adjacent and abutting the gate structure and overlying the first spacer material layer. The first spacer material layer and the second spacer material layer are then etched concurrently to form first and second spacers, respectively. An epitaxy region is formed (e.g., grown) on the substrate which includes an interface with each of the first and second spacers. The second spacer may be subsequently removed and the first spacer remain on the device decreases the aspect ratio for an ILD gap fill. An example composition of the first spacer is SiCN.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type and a semiconductor layer of a second conductivity type formed thereon. The semiconductor device also includes a body layer extending a first predetermined distance into the semiconductor layer of the second conductivity type and a pair of trenches extending a second predetermined distance into the semiconductor layer of the second conductivity type. Each of the pair of trenches consists essentially of a dielectric material disposed therein and a concentration of doping impurities present in the semiconductor layer of the second conductivity type and a distance between the pair of trenches define an electrical characteristic of the semiconductor device. The semiconductor device further includes a control gate coupled to the semiconductor layer of the second conductivity type and a source region coupled to the semiconductor layer of the second conductivity type.

Abstract: Disclosed is a thin-film transistor, which includes a gate terminal, a source terminal, and a drain terminal. The source terminal and the drain terminal are arranged side-by-aide above the gate terminal. The source terminal includes a first edge. The drain terminal includes a second edge. The first edge and the second edge face each other. The first edge and the second edge form therebetween a channel. The first edge and the second edge are both in a nonlinear form. A dimension of the channel in an extension of the first edge and the second edge is a width of the channel. The channel is narrowed from a middle thereof toward two ends in the widthwise direction of the channel. Light transmittance in each portion of the channel of the thin-film transistor is made consistent and the quality of the thin-film transistor is enhanced.

Abstract: A through via (144) contains a conductor (244, 276) passing through a substrate (140) for connection to an integrated circuit element. The through via consists of two segments (144.1, 144.2) formed from respective different sides (140.1, 140.2) of the substrate and meeting inside the substrate. Each segment is shorter than the entire via, so via formation is facilitated. The second segment is etched after deposition of an etch stop layer (214) into the first segment. Due to the etch stop layer, the first segment's depth does not have to be rigidly controlled. The conductor is formed by separate depositions of conductive material into the via from each side of the substrate. From each side, the conductor is deposited to a shallower depth than the via depth, so the deposition is facilitated. Other embodiments are also provided.

Abstract: A fan-out wafer-level-package (FOWLP) is provided. The FOWLP includes a redistribution layer (RDL) comprising a dielectric layer and a first metal layer; a passive device in the first metal layer; a first passivation layer covering a top surface of the RDL; a second passivation layer covering a bottom surface of the RDL; a chip mounted on the first passivation layer; a molding compound around the chip and on the first passivation layer; a via opening penetrating through the second passivation layer, the dielectric layer, and the second passivation layer, thereby exposing a terminal of the chip; a contact opening in the second passivation layer; and a second metal layer in the via opening and the contact opening to electrically connect one electrode of the passive device with the terminal of the chip.

Abstract: A semiconductor device includes a MISFET. The semiconductor device also includes a silicon nitride film 12 and a silicon nitride film 10 arranged on the silicon nitride film 12. The silicon nitride film 12 covers at least a portion of an upper part of a source/drain 8 of the MISFET and has a film thickness thinner than a height of a gate electrode 4. The source/drain 8 includes nickel silicide 9 on its boundary to the silicon nitride film 10. The silicon nitride film 10 is a stressed film. A tight adhering property between the silicon nitride film 12 and the surface of the source/drain 8 and that between the silicon nitride film 12 and the silicon nitride film 10 are rendered higher than a tight adhering property which would prevail when the silicon nitride film 10 be made to adhere tightly to the source/drain 8.

Abstract: A method for manufacturing a semiconductor device is disclosed. The method comprises: forming a T-shape dummy gate structure on the substrate; removing the T-shape dummy gate structure and retaining a T-shape gate trench; forming a T-shape metal gate structure by filling a metal layer in the T-shape gate trench. According to the semiconductor device manufacturing method disclosed in the present application, the overhang phenomenon and the formation of voids are avoided in the subsequent metal gate filling process by forming a T-shape dummy gate and a T-shape gate trench, and the device performance is improved.

Abstract: The present invention provides a Group III nitride semiconductor light-emitting device having a flat semiconductor layer, in which the stress applied to the light-emitting layer is relaxed. The light-emitting layer of the light-emitting device includes a well layer and a barrier layer comprising an AlGaN layer containing In. The light-emitting device has a pit extending from an n-type semiconductor layer to layers above the light-emitting layer. A pit diameter at an interface between the light-emitting layer and the n-type semiconductor layer is 120 nm to 200 nm. The barrier layer has an In concentration of 6.0×1019 cm?3.

Abstract: A pillar-type field effect transistor having low leakage current is provided. The pillar-type field effect transistor includes: a semiconductor body, source and drain formed in a semiconductor pillar; a gate insulating layer formed on a surface of the semiconductor body; a gate electrode formed on a surface of the gate insulating layer. The gate electrode includes a first gate electrode and a second gate electrode being electrically connected with the first gate electrode. The first gate electrode has a work function higher than that of the second gate electrode. Accordingly, the gate induced drain leakage (GIDL) can be reduced, so that an off-state leakage current can be greatly reduced.

Abstract: One illustrative method disclosed herein includes, among other things, forming an opening in a layer of insulating material so as to thereby expose at least a portion of a conductive contact, performing a selective deposition process to selectively form a layer of conductive material in the opening and on the conductive contact, performing an anneal process, depositing at least one conductive material above the selectively formed conductive material layer so as to over-fill the opening, and performing at least one planarization process so as to remove excess materials to thereby define a conductive via that is positioned in the opening and conductively coupled to the conductive contact.