Abstract: A semiconductor device and method of formation are provided. The semiconductor device includes a channel surrounding a dielectric tube and a gate surrounding the channel. The dielectric tube comprises a high dielectric constant material that has or conducts few to no carriers, such as electrons or holes. The presence of the dielectric tube confines carriers to the channel, which is in close proximity to the gate. The proximity of the channel, and the carriers therein, to the gate affords greater control to the gate over the carriers, thus allowing a length of the channel to be decreased while experiencing little to no short channel effects, such as current leakage through the channel.

Abstract: There are provided an organic light emitting display and a method of manufacturing the organic light emitting display. The organic light emitting display includes a lower substrate including a plurality of subpixel regions, a thin film transistor formed on the lower substrate, an organic light emitting element formed on the thin film transistor, an encapsulation unit for covering the organic light emitting element, a spacer formed on the encapsulation unit, an upper substrate disposed to face the lower substrate, and a desiccant between the lower substrate and the upper substrate. Various embodiments of the invention provide an organic light emitting display that enhances a viewing angle by minimizing a cell gap and minimizing a distortion of light, minimizes penetration of water or oxygen from the outside, and realizes a high resolution display by enhancing an aperture ratio, and a method of manufacturing the organic light emitting display.

Abstract: A light emitting device package may include a package body, a light emitting device on the package body, a first molding member that surrounds the light emitting device, and a second molding member having a hemi-spherical structure to surround the first molding member. The molding member includes a viscous material.

Abstract: A semiconductor device comprises a fin structure disposed over a substrate; a gate structure disposed over part of the fin structure; a source/drain structure, which includes part of the fin structure not covered by the gate structure; an interlayer dielectric layer formed over the fin structure, the gate structure, and the source/drain structure; a contact hole formed in the interlayer dielectric layer; and a contact material disposed in the contact hole. The fin structure extends in a first direction and includes an upper layer, wherein a part of the upper layer is exposed from an isolation insulating layer. The gate structure extends in a second direction perpendicular to the first direction. The contact material includes a silicon phosphide layer and a metal layer.

Abstract: The present invention generally relates to an RF MEMS DVC and a method for manufacture thereof. To ensure that undesired grain growth does not occur and contribute to an uneven RF electrode, a multilayer stack comprising an AlCu layer and a layer containing titanium may be used. The titanium diffuses into the AlCu layer at higher temperatures such that the grain growth of the AlCu will be inhibited and the switching element can be fabricated with a consistent structure, which leads to a consistent, predictable capacitance during operation.

Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include substrate including electrical connection circuitry therein, ground circuitry on, or at least partially in the substrate, the ground circuitry at least partially exposed by a surface of the substrate, a die electrically connected to the connection circuitry and the ground circuitry, the die on the substrate, a conductive material on a die backside, and a conductive paste or one or more wires electrically connected to the ground circuitry and the conductive material.

Abstract: Gate contact structures disposed over active portions of gates and methods of forming such gate contact structures are described. For example, a semiconductor structure includes a substrate having an active region and an isolation region. A gate structure has a portion disposed above the active region and a portion disposed above the isolation region of the substrate. Source and drain regions are disposed in the active region of the substrate, on either side of the portion of the gate structure disposed above the active region. A gate contact structure is disposed on the portion of the gate structure disposed above the active region of the substrate.

Abstract: An integrated circuit with a SAR SRAM cell with power routed in metal-1. An integrated circuit with a SAR SRAM cell that has power routed in Metal-1 and has metal-1 and metal-2 integrated circuit and SAR SRAM cell patterns which are DPT compatible. A process of forming an integrated circuit with a SAR SRAM cell with DPT compatible integrated circuit and SAR SRAM cell metal-1 and metal-2 patterns.

Abstract: A package, includes a cup-shaped resin component having a bottom surface and side walls that surround the bottom surface, an opening which is opened at an upper part of the side walls, a pair of leads exposed on part of the bottom surface, and a reflective film, the resin component having a 3-D shape defined by an X axis, a Y axis and a Z axis, the outer surface of the side walls that has a recess which is recessed in the Z axis direction and arranged in a position corresponding to the opening, and the reflective film being disposed in the recess.

Abstract: A semiconductor device includes a gate dielectric layer and a gate electrode formed on the gate dielectric layer. The gate electrode includes a first metal layer, a second metal layer, and a third metal layer. The first metal layer includes an oxygen-gettering composition. The second metal layer includes oxygen. The third metal layer includes an interface with a polysilicon layer.

Abstract: An exemplary method includes forming a dummy gate structure over a substrate and forming a set of spacers adjacent to the dummy gate structure. The set of spacers includes spacer liners disposed on sidewalls of the dummy gate structure and main spacers disposed on the spacer liners. The spacer liners include silicon and carbon. The method further includes forming source/drain epitaxy regions over the substrate. The source/drain epitaxy regions are disposed adjacent to the set of spacers, such that the dummy gate structure is disposed between the source/drain epitaxy regions. The method further includes removing the main spacers after forming the source/drain epitaxy regions. The method further includes replacing the dummy gate structure with a gate structure, where the replacing includes removing the dummy gate structure to form a trench defined by the spacers liners, such that the gate structure is formed in the trench.

Abstract: An electronic system without using solder balls between electrical components, and without using interposer between chips and package substrate, without using a discrete system board for the chip package to mount. At least one chip is wrapped by molding material, a first redistribution circuitry is built on a bottom side of the molding material. A plurality of first inverse T-shaped metals of the first redistribution circuitry are electrically coupled to the at least one chip; a second redistribution circuitry is built on a bottom side of the first redistribution circuitry. A plurality of second inverse T-shaped metals of the second redistribution circuitry are electrically coupled to the first redistribution circuitry. Either the first redistribution circuitry or the second redistribution circuitry has at least a first extension extended beyond a corresponding side surface of the molding material to electrically couple to at least one device.

Abstract: An integrated circuit with a SAR SRAM cell with power routed in metal-1. An integrated circuit with a SAR SRAM cell that has power routed in Metal-1 and has metal-1 and metal-2 integrated circuit and SAR SRAM cell patterns which are DPT compatible. A process of forming an integrated circuit with a SAR SRAM cell with DPT compatible integrated circuit and SAR SRAM cell metal-1 and metal-2 patterns.

Abstract: An image sensor includes: a light receiving section suitable for generating photocharges in response to incident light; and a driving section including a source follower transistor suitable for generating an output voltage corresponding to a reference voltage in response to the photocharges. The source follower transistor includes: a stack structure formed by sequentially stacking a first conductive layer, an insulating layer and a second conductive layer; an open portion formed through the second conductive layer and the insulating layer so as to expose the first conductive layer; a channel layer formed along the surface of the open portion so as to be connected to the first conductive layer and the second conductive layer; and a gate is connected to the light receiving section and which is formed over the channel layer so as to overlap the second conductive layer.

Abstract: Methods for forming a string of memory cells, apparatuses having a string of memory cells, and systems are disclosed. One such method for forming a string of memory cells forms a source material over a substrate. A capping material may be formed over the source material. A select gate material may be formed over the capping material. A plurality of charge storage structures may be formed over the select gate material in a plurality of alternating levels of control gate and insulator materials. A first opening may be formed through the plurality of alternating levels of control gate and insulator materials, the select gate material, and the capping material. A channel material may be formed along the sidewall of the first opening. The channel material has a thickness that is less than a width of the first opening, such that a second opening is formed by the semiconductor channel material.

Abstract: An organic EL device includes an organic light-emitting layer provided above a first substrate; a protective layer provided above the organic light-emitting layer; a color filter provided on the protective layer; and a second substrate adhered to the color filter via an adhesive, in which a colored layer includes a first colored layer, a second colored layer, and a third colored layer, the color filter includes a first region in which the first colored layer, the second colored layer, and the third colored layer are respectively arranged as single colors and a second region in which the first colored layer, the second colored layer, and the third colored layer are arranged in a layered manner, and a height difference-relieving layer is provided between the color filter and the adhesive.

Abstract: An electronic system without using solder balls between electrical components, and without using interposer between chips and package substrate, without using a discrete system board for the chip package to mount. A chip is wrapped by molding material, a first redistribution circuitry is built on a bottom side of the molding material; a second redistribution circuitry is built on a bottom side of the first redistribution circuitry. A third redistribution circuitry is built on a bottom side of the second redistribution circuitry. Plated metal vias are configured between each two of the electrical components.

Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

Abstract: The inventive concepts relate to a semiconductor memory device. The semiconductor memory device includes a substrate including a circuit region and first and second connection regions respectively disposed at both sides of the circuit region opposite to each other, a logic structure including a logic circuit disposed on the circuit region and a lower insulating layer covering the logic circuit, and a memory structure on the logic structure. The logic circuit includes a first page buffer disposed adjacently to the first connection region and a second page buffer disposed adjacently to the second connection region. The memory structure includes bit lines extending onto at least one of the first and second connection regions.

Abstract: A thermodynamic RAM circuit composed of a group of AHaH (Anti-Hebbian and Hebbian) computing circuits that form one or more kT-RAM circuits. The AHaH computing circuits can be configured as an AHaH computing stack. The kTRAM circuit(s) can include one or core kT-Cores, each partitioned into AHaH nodes of any size via time multiplexing. The kT-Core couples readout electrodes together to form a larger combined kT-Core. AHaH Computing is the theoretical space encompassing the capabilities of AHaH nodes. At this level of development, solutions have been found for problems as diverse as classification, prediction, anomaly detection, clustering, feature learning, actuation, combinatorial optimization, and universal logic.