Patents Examined by Vu A. Le
  • Patent number: 10929703
    Abstract: Respective actions are taken by two electronic devices based upon information captured by cameras of the devices. An image of a subject is captured with a first camera equipped in the first electronic device with a second camera equipped in the second electronic device. Form feature information of the subject is then recognized from the captured images. The first electronic device performs a first operation and the second electronic device performs a second operation responsive to recognizing the form feature of the subject.
    Type: Grant
    Filed: January 14, 2016
    Date of Patent: February 23, 2021
    Assignee: Lenovo (Singapore) PTE. LTD.
    Inventors: Hiroshi Itoh, Toshiaki Jozawa
  • Patent number: 10931851
    Abstract: Systems and methods are disclosed for image signal processing. For example, methods may include receiving a first image from a first image sensor; receiving a second image from a second image sensor; determining an electronic rolling shutter correction mapping for the first image and the second image; determining a parallax correction mapping based on the first image and the second image for stitching the first image and the second image; determining a warp mapping based on the parallax correction mapping and the electronic rolling shutter correction mapping, wherein the warp mapping applies the electronic rolling shutter correction mapping after the parallax correction mapping; applying the warp mapping to image data based on the first image and the second image to obtain a composite image; and storing, displaying, or transmitting an output image that is based on the composite image.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: February 23, 2021
    Assignee: GoPro, Inc.
    Inventors: Bruno C├ęsar Douady-Pleven, Antoine Meler, Christophe Clienti
  • Patent number: 10924097
    Abstract: Examples described herein include command latency shifters which may include a plurality of registers arranged in a folded topology.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: February 16, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Kazutaka Miyano
  • Patent number: 10923648
    Abstract: Various embodiments may relate to a memory cell. The memory cell may include a first cell electrode, a first insulator layer and a first magnetic free layer between the first cell electrode and the first insulator layer. The memory cell may also include a second cell electrode, a second insulator layer, and a second magnetic free layer between the second cell electrode and the second insulator layer. A magnetic pinned layer may be between the first insulator layer and the second insulator layer. A direction of magnetization of the first magnetic free layer may be changeable in response to a current flowing between a first end and a second end of the first cell electrode. A direction of magnetization of the second magnetic free layer may be changeable in response to a current flowing between a first end and a second end of the second cell electrode.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: February 16, 2021
    Assignee: Agency for Science, Technology and Research
    Inventors: Karim Ali Abdeltawwab Ahmed, Sunny Yan Hwee Lua, Fei Li
  • Patent number: 10922262
    Abstract: Apparatuses and methods of data transmission between semiconductor chips are described. An example apparatus includes: a data bus inversion (DBI) circuit that receives first, second and third input data in order, and further provides first, second and third output data, either with or without data bus inversion. The DBI circuit includes a first circuit that latches the first input data and the third input data; a second circuit that latches the second input data; a first DBI calculator circuit that performs first DBI calculation on the latched first input data and the latched second input data responsive to the first circuit latching the first input data and the second circuit latching the second input data, respectively; and a second DBI calculator circuit that performs second DBI calculation on the latched second data and the latched third input data responsive to the first circuit latching the third input data.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: February 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Yuki Ebihara, Seiji Narui
  • Patent number: 10923655
    Abstract: Disclosed are a variable resistance memory device and a method of manufacturing the same. The device comprises a first conductive line extending in a first direction, a second conductive line extending in a second direction intersecting the first direction, a memory cell at an intersection between the first conductive line and the second conductive line, a first electrode between the first conductive line and the memory cell, and a second electrode between the second conductive line and the memory cell. The memory cell comprises a switching pattern, an intermediate electrode, a first resistivity control pattern, and a variable resistance pattern that are connected in series between the first conductive line and the second conductive line. Resistivity of the first resistivity control pattern is less than resistivity of the second electrode.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: February 16, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-Hyun Jeong, Ilmok Park, Si-Ho Song
  • Patent number: 10923317
    Abstract: Methods and systems for detecting defects in a logic region on a wafer are provided. One method includes acquiring information for different types of design-based care areas in a logic region of a wafer. The method also includes designating the different types of the design-based care areas as different types of sub-regions and, for a localized area within the logic region, assigning two or more instances of the sub-regions located in the localized area to a super-region. In addition, the method includes generating one scatter plot for all of the two or more instances of the sub-regions assigned to the super-region. The one scatter plot is generated with different segmentation values for the output corresponding to the different types of the sub-regions. The method further includes detecting defects in the sub-regions based on the one scatter plot.
    Type: Grant
    Filed: August 18, 2019
    Date of Patent: February 16, 2021
    Assignee: KLA Corp.
    Inventors: Junqing Huang, Paul Russell, Hucheng Lee, Kenong Wu
  • Patent number: 10922786
    Abstract: An interpolation unit generates an interpolation image from an original image. An index value calculation unit calculates an index value indicating the feature of a pixel position in a region of interest of the original image based on pixel values of corresponding pixel positions, which are a plurality of pixel positions of the interpolation image, corresponding to the pixel position included in the region of interest in the original image. A reflection unit reflects the index value calculated by the index value calculation unit at the pixel position of a bleeding region of the original image.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: February 16, 2021
    Assignee: FUJIFILM Corporation
    Inventor: Yu Hasegawa
  • Patent number: 10914690
    Abstract: A method of characterizing a part including obtaining an X-ray tomography image of the part and then a step of correlating the image with a reference wherein the correlation step includes searching among a predefined set of X-ray tomography image transformations for a transformation that minimizes the difference between the image and the reference in order to characterize the inside of the part.
    Type: Grant
    Filed: December 9, 2014
    Date of Patent: February 9, 2021
    Assignees: SAFRAN AIRCRAFT ENGINES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, ECOLE NORMALE SUPERIEURE DE CACHAN
    Inventors: Julien Schneider, Francois Hild, Hugo Leclerc, Stephane Roux
  • Patent number: 10902911
    Abstract: Threshold switching devices demonstrating transient current protection through both insulation and repair current mechanisms, including associated systems and methods, are provided and discussed.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: January 26, 2021
    Assignee: Intel Corporation
    Inventors: Davide Mantegazza, Sandeep Guliani, Balaji Srinivasan, Kiran Pangal
  • Patent number: 10902929
    Abstract: Methods, systems, and devices related to zone swapping for wear leveling memory are described. A memory device can perform access operations by mapping respective logical zones associated with respective logical addresses (e.g., of an access command) to respective zones of the memory device. As the memory device receives access commands and accesses respective zones, some zones may undergo a disproportionate amount of access operations relative to other zones. Accordingly, the memory device may swap data stored in some disproportionately accessed zones. The memory device can update a correspondence of respective logical zones associated with the zones based on swapping the data so that later access operations access the desired data.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: January 26, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Joseph T. Pawlowski
  • Patent number: 10902901
    Abstract: Methods, systems, and devices for access line management for an array of memory cells are described. Some memory devices may include a plate that is coupled with memory cells associated with a plurality of digit lines and/or a plurality of word lines. Because the plate is coupled with a plurality of digit lines and/or word lines, unintended cross-coupling between various components of the memory device may be significant. To mitigate the impact of unintended cross-coupling between various components, the memory device may float unselected word lines during one or more portions of an access operation. Accordingly, a voltage of each unselected word line may relate to the voltage of the plate as changes in plate voltage may occur.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: January 26, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Patent number: 10896717
    Abstract: An example apparatus includes an array of memory cells coupled to an array power supply and a controller. The controller may be configured to cause a data value to be stored in at least one memory cell of the array of memory cells while the array of memory cells is operating in a first power state and a determination to be made that a change in a power status to a computing system coupled to the array of memory cells has occurred, wherein the change in the power status of the computing system is characterized by the computing device operating in a reduced power state. Responsive to the determination, the controller may be configured to cause the array power supply to be disabled to operate the array of memory cells in a second power state.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: January 19, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Scott J. Derner, Christopher J. Kawamura
  • Patent number: 10896713
    Abstract: Methods, systems, and devices for access line management for an array of memory cells are described. Some memory devices may include a plate that is coupled with memory cells associated with a plurality of digit lines and/or a plurality of word lines. Because the plate is coupled with a plurality of digit lines and/or word lines, unintended cross-coupling between various components of the memory device may be significant. To mitigate the impact of unintended cross-coupling between various components, the memory device may float unselected word lines during one or more portions of an access operation. Accordingly, a voltage of each unselected word line may relate to the voltage of the plate as changes in plate voltage may occur.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: January 19, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Daniele Vimercati
  • Patent number: 10891777
    Abstract: The present invention relates to an ultrasound imaging system comprising an ultrasound probe having a transducer array configured to provide an ultrasound receive signal. The system further comprises a B-mode volume processing unit configured to generate a B-mode volume based on the ultrasound receive signal, and a B-mode image processing unit configured to provide a current B-mode image based on the B-mode volume. The system further comprises a memory configured to store a previously acquired 3D-vessel map. Also, the system comprises a registration unit configured to register the previously acquired 3D-vessel map to the B-mode volume and to select a portion of the 3D-vessel map corresponding to the current B-mode image. Further, the system comprises a display configured to display an ultrasound image based on the current B-mode image and the selected portion of the 3D-vessel map.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: January 12, 2021
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventors: Gary Cheng-How Ng, James Robertson Jago, Andrew Lee Robinson
  • Patent number: 10892022
    Abstract: Methods of operating a memory, and memories configured to perform similar methods, might include initiating discharge of a global access line that is connected to a local access line through a transistor, and electrically floating a control gate of the transistor, in response to a supply voltage decreasing to a first threshold, and initiating discharge of the control gate of the transistor in response to the supply voltage decreasing to a second threshold lower than the first threshold.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: January 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kalyan C. Kavalipurapu, Xiaojiang Guo
  • Patent number: 10885992
    Abstract: A memory system includes: a memory device; a run-time bad block detector suitable for storing information of super memory blocks, each including a run-time bad block, in a bad list; a bit-map manager suitable for generating a bit-map representing integrity information of memory blocks in each of the super memory blocks; a short super block manager suitable for designating, among the super memory blocks, a super memory block having a number of run-time bad blocks less than or equal to a threshold as a short super memory block based on the bad list and the bit-map, whenever a logical unit configuration command is received from a host; and a processor suitable for controlling the memory device to simultaneously access normal blocks among the memory blocks forming the designated short super memory block and to perform a normal operation, based on the bit-map.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: January 5, 2021
    Assignee: SK hynix Inc.
    Inventor: Joo-Young Lee
  • Patent number: 10885643
    Abstract: An image processing apparatus configured to calculate deformation between a first image and a second image includes a calculation order determination unit that determines calculation order of a plurality of partial regions into which the second image is divided, a calculation unit that calculates the deformation between the first image and the second image for each of the plurality of partial regions in the determined calculation order of the plurality of partial regions, a deformed image generation unit that generates a deformed image by deforming the first image based on the calculated deformation of the plurality of partial regions, and a display control unit that causes a display unit to display the generated deformed image.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: January 5, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventors: Itaru Otomaru, Kazuhiro Miyasa, Kiyohide Satoh
  • Patent number: 10885971
    Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: January 5, 2021
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, Ming Li
  • Patent number: 10878570
    Abstract: A mechanism is provided in a data processing system comprising a processor and a memory, the memory comprising instructions that are executed by the processor to specifically configure the processor to implement a knockout autoencoder engine for detecting anomalies in biomedical images. The mechanism trains a neural network to be used as a knockout autoencoder that predicts an original based on an input image. The knockout autoencoder engine provides a biomedical image as the input image to the neural network. The neural network outputs a probability distribution for each pixel in the biomedical image. Each probability distribution represents a predicted probability distribution of expected pixel values for a given pixel in the biomedical image. An anomaly detection component executing within the knockout autoencoder engine determines a probability that each pixel has an expected value based on the probability distributions to form a plurality of expected pixel probabilities.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: December 29, 2020
    Assignee: International Business Machines Corporation
    Inventor: Paul Dufort