Abstract: Memory devices have an array of elements in two or more dimensions. The memory devices use multiple access lines arranged in a grid to access the memory devices. Memory cells are located at intersections of the access lines in the grid. Drivers are used for each access line and configured to transmit a corresponding signal to respective memory cells of the plurality of memory cells via a corresponding access line. The memory devices also include compensation circuitry configured to determine which driving access lines driving a target memory cell of the plurality of memory cells has the most distance between the target memory cell and a respective driver. The plurality of access lines comprise the driving access lines. The compensation circuitry also is configured to output compensation values to adjust the voltages of the driving access lines based on a polarity of the voltage of the longer driving access line.

Abstract: A system may be configured to collect geospatial features (in vector form) such that a software application is operable to edit an object represented by at least one vector. Some embodiments may: generate, via a trained machine learning model, a pixel map based on an aerial or satellite image; convert the pixel map into vector form; and store the vectors. This conversion may include a raster phase and a vector phase. A system may be configured to obtain another image, generate another pixel map based on the other image, convert the other pixel map into vector form, and compare the vectors to identify changes between the images. Some implementations may cause identification, based on a similarity with converted vectors, of a more trustworthy set of vectors for subsequent data source conflation.

Abstract: The present disclosure relates to a memory device comprising a plurality of memory cells, each memory cell being programmable to a logic state corresponding to a threshold voltage exhibited by the memory cell in response to an applied voltage, and a logic circuit portion operatively coupled to the plurality of memory cells, wherein the logic circuit portion is configured to scan memory addresses of the memory device, and to generate seasoning pulses to be applied to the addressed pages of the memory device. A related electronic system and related methods are also disclosed.

Abstract: Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space.

Abstract: Devices, systems and methods for adaptively controlling a reset current of a memory cell are described. A system comprises: a mirror circuit with one branch coupled with a top electrode of the memory cell and the other branch coupled with one end of a resistive reference, and wherein a bottom electrode of the memory cell is coupled to a reference potential, the other end of the resistive reference is provided with a first electric potential; a control circuit; and a feedback circuit for feeding an electric potential to the top electrode of the memory cell.

Abstract: Disclosed is a CT image generation method for attenuation correction of PET images. According to the method, a CT image and a PET image at T1 and a PET image at T2 are acquired and input into a trained deep learning network to obtain a CT image at T2; the CT image can be applied to the attenuation correction of the PET image, thereby obtaining more an accurate PET AC (Attenuation Correction) image. According to the CT image generation method for attenuation correction of PET images, the dosage of X-rays received by a patient in the whole image acquisition stage can be reduced, and physiological and psychological pressure of the patient is relieved. In addition, the later image acquisition only needs a PET imaging device, without the need of PET/CT device, cost of imaging resource distribution can be reduced, and the imaging expense of the whole stage is reduced.

Abstract: A farming machine moves through a field and includes an image sensor that captures an image of a plant in the field. A control system accesses the captured image and applies the image to a machine learned plant identification model. The plant identification model identifies pixels representing the plant and categorizes the plant into a plant group (e.g., plant species). The identified pixels are labeled as the plant group and a location of the pixels is determined. The control system actuates a treatment mechanism based on the identified plant group and location. Additionally, the images from the image sensor and the plant identification model may be used to generate a plant identification map. The plant identification map is a map of the field that indicates the locations of the plant groups identified by the plant identification model.

Abstract: A method for generating and evaluating N-to-1 mappings, between spatial point sets in nD, n=2 or 3 implemented on a computing device comprising a programmable general purpose processor and a programmable data-parallel coprocessor and a memory coupled with them. Embodiments comprises using the computing device to receive a first and a second spatial point sets, the first spatial point set comprising a first non-empty portion of non-isolated points and a second non-empty portion of constrained points, an array of fixed correspondents for the second non-empty portion, and a CCISS or padded CCISS between the first non-isolated portion and the second spatial point set, and use these to generate an array of N-to-1 mappings between the first portion of non-isolated points and the second spatial point set, an array of overall distance measures for the array of N-to-1 mappings, and an optimal N-to-1 mapping with the lowest overall distance measure.

Abstract: A resistive memory apparatus including bit lines, word lines, a memory array, bypass paths, select circuits, and a switch circuit is provided. The word lines are respectively crossed with the bit lines. The memory array includes memory elements. One end of each of the memory elements is coupled to the corresponding word line, and another end of each of the memory elements is coupled between a first node and a second node on the corresponding bit line. Each of the bypass paths is connected in parallel with the corresponding bit line between the first node point and the second node. Each of the select circuits is coupled to the corresponding bit line and bypass path, and configured to select the coupled bit line or bypass path. The switch circuit is coupled to the word lines, and configured to select one of the word lines.

Abstract: In an embodiment, a memory controller in an integrated circuit may generate refreshes for one or more DRAMs coupled to the integrated circuit according to a refresh rate. The integrated circuit may include one or more temperature sensors. A rate of change of the temperature may be determined from the temperature sensors. If the rate is greater than a threshold, the memory controller may generate refreshes according to a refresh rate specified by the DRAMs. If the rate is less than the threshold, the memory controller may generate refreshes at a reduced refresh rate.

Abstract: A phase-change memory (10) for the non-volatile storage of binary contents stores the binary contents electrically and/or optically in a non-volatile manner by locally switching a material (18) between an amorphous and a crystalline phase. The state with respect to the electrical conductivity of the material (18) and/or the reflection properties of the material (18) determines the information content of the phase-change memory (10). A method for non-volatile storage of binary contents in a phase-change memory (10), which stores the binary contents electrically and/or optically in a non-volatile manner by locally switching a material (18) between an amorphous and a crystalline phase, whereby the state with respect to the electrical conductivity of the material (18) and/or the reflection properties of the material (18) determines the information content of the phase-change memory (10).

Abstract: Embodiments relate to an image processing circuit comprising a noise reduction circuit configurable to perform bilateral filtering on demosaiced and resampled image data, or on raw image data, based on the operating mode of the image processing circuit. The noise reduction circuit filters received image data based upon directional taps, by selecting, for each pixel, a set of neighbor pixels, and comparing values of the set of neighbor pixels to determine whether the pixel lies on a directional edge. For raw images, the noise reduction circuit selects the set of neighbor pixels to include a plurality of pixels of the same color channel as the pixel, and one or more additional pixels of a different color channel, where color values for the one or more additional pixels are determined by interpolating color values of two or more adjacent pixels of the same color channel as the pixel.

Abstract: A method including receiving, from a C-arm device, a plurality of fluoroscopic images of a lung, wherein each fluoroscopic image is obtained with the C-arm device positioned at a particular pose of a plurality of poses traversed by the C-arm device while the C-arm device is moved through a range of motion including a range of rotation, the range of rotation encompassing a sweep angle between 45 degrees and 120 degrees; generating an enhanced tomographic image of the lung, by utilizing: a trained machine learning model and the plurality of fluoroscopic images; and outputting a representation of the enhanced tomographic image, wherein, when tested by a method in which: the lung includes a lesion smaller than 30 millimeters, and the representation is an axial slice showing a boundary of the lesion, the lesion has a contrast-to-noise value of at least 5 as compared to a background of the representation.

Abstract: According to an embodiment, a phase-change memory device comprises: an upper electrode and a lower electrode; a phase-change layer in which a crystal state thereof is changed by heat supplied by the upper electrode and the lower electrode; and a selector which selectively switches the heat supplied by the upper electrode and the lower electrode to the phase-change layer, wherein the selector is formed of a compound which includes a transition metal in the phase-change material so as to have a high resistance when the crystalline state of the selector is crystalline and so as to have a low resistance when the crystalline state of the selector is non-crystalline.

Abstract: A deep learning (DL) convolution neural network (CNN) reduces noise in positron emission tomography (PET) images, and is trained using a range of noise levels for the low-quality images having high noise in the training dataset to produce uniform high-quality images having low noise, independently of the noise level of the input image. The DL-CNN network can be implemented by slicing a three-dimensional (3D) PET image into 2D slices along transaxial, coronal, and sagittal planes, using three separate 2D CNN networks for each respective plane, and averaging the outputs from these three separate 2D CNN networks. Feature-oriented training can be implemented by segmenting each training image into lesion and background regions, and, in the loss function, applying greater weights to voxels in the lesion region. Other medical images (e.g. MRI and CT) can be used to enhance resolution of the PET images and provide partial volume corrections.

Abstract: Provided herein may be a resistive memory device and a method of operating the resistive memory device. The resistive memory device may include strings coupled between one or more source lines and one or more bit lines, each string including a set of one or more resistive memory cells, one or more word lines respectively coupled to the set of one or more resistive memory cells; and a voltage generator configured to control a level of a turn-on voltage to be applied to one or more unselected word lines among the one or more word lines depending on a program target state of a subset of resistive memory cells including one or more resistive memory cells selected from among the set of one or more resistive memory cells.

Abstract: Resistive memory devices are provided which are configured to mitigate resistance drift. A device comprises a phase-change element, a resistive liner, a first electrode, a second electrode, and a third electrode. The resistive liner is disposed in contact with a first surface of the phase-change element. The first electrode is coupled to a first end portion of the resistive liner. The second electrode is coupled to a second end portion of the resistive liner. The third electrode is coupled to the first surface of the phase-change element.

Abstract: A method for programming a phase change memory including a first layer of a phase change material capable of switching between a crystalline and an amorphous state and vice versa, the method including applying a programming current through the first layer so that an evolution of the areal density of this current as a function of time t decreases from a first level, between a first time and a second time, following a first evolution in time respecting, or being close to J 0 ? ( t ) = K t where K is a constant.

Abstract: Methods, systems, and devices for a refresh operation of a memory cell are described. A memory device may include a plurality of rows of memory cells. Each row of memory cells may undergo a quantity of access operations (e.g., read operations, write operations). During a read operation, a logic state of one or more memory cells may be determined by applying a read pulse having a first polarity. Based on the one or more memory cells storing a particular logic state (e.g., a first logic state), a refresh operation may be performed. During a refresh operation, a refresh pulse having a second polarity (e.g., a different polarity than the first polarity) may be applied to the one or more memory cells.

Abstract: A method for setting memory elements in a plurality of states includes applying a set signal to a memory element to transition the memory element from a low-current state to a high-current state; applying a partial reset signal to the memory element to transition the memory element from the high-current state to a state between the high-current state and the low-current state; determining whether the state corresponds to a predetermined state; and applying one or more additional partial reset signals to the memory element until the state corresponds to the predetermined current state. The memory element may be coupled in series with a transistor, and a voltage control circuit may apply voltages to the transistor to set and partially reset the memory element.