Patents Examined by Vu Le
  • Patent number: 10176612
    Abstract: In a method for retrieval of similar findings from a hybrid image dataset, a database of hotspots is prepared, wherein the hotspots are identified by binary strings encoding descriptors, and identify binary strings stored in the database are identified that resemble a new binary string.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: January 8, 2019
    Assignee: Siemens Medical Solutions USA, Inc.
    Inventors: Matthew David Kelly, David Schottlander, Ludovic Sibille
  • Patent number: 10175948
    Abstract: A system according to one embodiment includes a pinned layer; a spacer layer above the pinned layer; a free layer above the spacer layer; a heating device, for heating the free layer to induce a paramagnetic thermal instability in the free layer whereby a magnetization of the free layer randomly switches between different detectable magnetic states upon heating thereof; and a magnetoresistance detection circuit for detecting an instantaneous magnetic state of the free layer.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: January 8, 2019
    Assignee: Western Digital Technologies, Inc.
    Inventors: Patrick M. Braganca, Jordan A. Katine, Yang Li, Neil L. Robertson, Qingbo Wang, Haiwen Xi
  • Patent number: 10176881
    Abstract: A non-volatile memory device includes: a memory cell array including a memory cell string including a ground selection transistor and a plurality of serially connected non-volatile memory cells; a ground selection line connected to the ground selection transistor and a plurality of word lines connected to the plurality of memory cells; a voltage generator configured to generate a program verification voltage and a read voltage applied to the plurality of word lines; and a control circuit configured to control a compensation for the program verification voltage based on a program verification temperature offset, and control a to compensation for the read voltage based on a read temperature offset.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: January 8, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jisuk Kim, Il Han Park, Se Hwan Park
  • Patent number: 10168712
    Abstract: A computing device of a first vehicle may receive a first image and a second image of a second vehicle having flashing light signals. The computing device may determine, in the first image and the second image, an image region that bounds the second vehicle such that the image region substantially encompasses the second vehicle. The computing device may determine a polar grid that partitions the image region in the first image and the second image into polar bins, and identify portions of image data exhibiting a change in color and a change in brightness between the first image and the second image. The computing device may determine a type of the flashing light signals and a type of the second vehicle; and accordingly provide instructions to control the first vehicle.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: January 1, 2019
    Assignee: Waymo LLC
    Inventors: Wan-Yen Lo, David Ian Franklin Ferguson, Abhijit Ogale
  • Patent number: 10169647
    Abstract: A method and system for automatically inferring a subject's body position in a two-dimensional image produced by a medical-imaging system are disclosed. The image is labeled with a body position selected from a semantically meaningful set of candidate positions sequenced in order of their relative locations in a subject's body. A processor performs procedures that each identify a class of image features related to pixel intensity, such as a histogram of gradients, local binary patterns, or Haar-like features. A second set of procedures employs applications of a pretrained convolutional neural network that has learned to recognize features of a specific class of medical images. The results of both types of procedures are then mapped by a pretrained support-vector machine onto candidate image labels, which are mathematically combined into a single, semantically meaningful, label most likely to identify a body position of the subject shown by the image.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Yaniv Gur, Mehdi Moradi, Tanveer F. Syeda-Mahmood, Hongzhi Wang
  • Patent number: 10163477
    Abstract: A memory array having a first port and a second port is disclosed. The memory array includes: a first memory cell, wherein access to the first memory cell through the first port is controlled by a first word line, and access to the first memory cell through the second port is controlled by a second word line; a second memory cell, wherein access to the second memory cell through the first port is controlled by the first word line, and access to the second memory cell through the second port is controlled by the second word line; and a disturb detector, used to generate a disturb detected signal for indicating whether the first memory cell and the second memory cell are accessed at a same time. A memory array having a write assistor is also disclosed.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Sanjeev Kumar Jain, Ali Taghvaei, Atul Katoch
  • Patent number: 10163512
    Abstract: A semiconductor device and or method of operating the same may be provided. The semiconductor device may include a pass circuit unit configured to connect global signal lines to signal lines to set voltage levels of the signal lines.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: December 25, 2018
    Assignee: SK hynix Inc.
    Inventors: Jung Hwan Lee, Se Chun Park
  • Patent number: 10163493
    Abstract: Embodiments of the present invention provide systems and methods for re-balancing the stability of a SRAM cell. Embodiments of the present invention identify SRAM cells with negative voltage threshold margins and write a “zero” state bit with in the bi-stable flip-flop of the SRAM. Raising the voltage of the CMOS set containing the “zero” state bit and selective transistor biasing, skews the “zero” state bit towards the complementary “one” state bit. This induces an increase voltage thresholds of the identified SRAM cells.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: December 25, 2018
    Assignee: International Business Machines Corporation
    Inventors: William V. Huott, Chandrasekharan Kothandaraman, Adam J. McPadden, Uma Srinivasan, Stephen Wu
  • Patent number: 10157461
    Abstract: The present invention provides a cell evaluation device, a cell evaluation method and a non-transitory computer readable recording medium storing a cell evaluation program capable of evaluating an evaluation target cell. The cell evaluation device includes an image acquisition unit that acquires a cell image obtained by imaging a cell group; a cell evaluation unit that specifies an evaluation target cell and peripheral cells around the evaluation target cell in the cell group, and evaluates the evaluation target cell based on evaluation results of the peripheral cells; and a boundary setting unit that sets a boundary in the cell image based on a state of the cell group, in which when specifying the peripheral cells, the cell evaluation unit specifies only cells that are present in a divided region where the evaluation target cell is present among plural divided regions divided by the boundary, as the peripheral cells.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: December 18, 2018
    Assignee: FUJIFILM Corporation
    Inventor: Kenta Matsubara
  • Patent number: 10157663
    Abstract: Methods, devices, arrays and systems for reducing standby power for a floating body memory array. One method includes counting bits of data before data enters the array, wherein the counting includes counting at least one of: a total number of bits at state 1 and a total number of all bits; a total number of bits at state 0 and the total number of all bits; or the total number of bits at state 1 and the total number of bits at state 0. This method further includes detecting whether the total number of bits at state 1 is greater than the total number of bits at state 0; setting an inversion bit when the total number of bits at state 1 is greater than the total number of bits at state 0; and inverting contents of all the bits of data before writing the bits of data to the memory array when the inversion bit has been set.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: December 18, 2018
    Assignee: Zeno Semiconductor, Inc.
    Inventors: Benjamin S. Louie, Yuniarto Widjaja
  • Patent number: 10157652
    Abstract: A magnetic device configured to perform an analog adder circuit function and including a plurality of magnetic units. Each magnetic unit includes n magnetic tunnel junctions electrically connected in series via a current line. Each magnetic tunnel junction includes a storage magnetic layer having a storage magnetization, a sense magnetic layer having a sense magnetization, and a tunnel barrier layer. Each magnetic unit also includes n input lines, each being configured to generate a magnetic field adapted for varying a direction of the sense magnetization and a resistance of the n magnetic tunnel junctions, based on an input. Each of the n magnetic units is configured to add said n inputs to generate an output signal that varies in response to the n resistances.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: December 18, 2018
    Assignee: CROCUS TECHNOLOGY SA
    Inventor: Quentin Stainer
  • Patent number: 10157666
    Abstract: A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sahil Preet Singh, Jung-Hsuan Chen, Yen-Huei Chen, Avinash Chander, Albert Ying
  • Patent number: 10154782
    Abstract: An apparatus for producing a fundus image includes: a processor and a memory; an illumination component including a light source and operatively coupled to the processor; a camera including a lens and operatively coupled to the processor, wherein the memory stores instructions that, when executed by the processor, cause the apparatus to: execute an automated script for capture of the fundus image; and allow for manual capture of the fundus image.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: December 18, 2018
    Assignee: Welch Allyn, Inc.
    Inventors: Richard M. Farchione, Austin Gardner, Scott P. Gucciardi, Allen R. Hart, Eric P. Jensen, Thomas A. Myers, Salvin J. Strods, Ynjiun P. Wang, Charles E. Witkowski, II
  • Patent number: 10157660
    Abstract: A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: December 18, 2018
    Assignee: Rambus Inc.
    Inventors: Scott C. Best, Ming Li
  • Patent number: 10157674
    Abstract: A soft erase method of a memory device including applying a program voltage to a first memory cell in at least one of program loops when a plurality of program loops are performed to program the first memory cell into a Nth programming state, wherein the first memory cell is included in a selected memory cell string connected to a selected first bit line and is connected to a selected word line; and soft erasing a second memory cell by applying, in a first verification interval, a read voltage for verifying a programming state of the first memory cell to the selected word line and applying a first prepulse to a gate of a string select transistor of each of a plurality of unselected memory cell strings connected to the first bin line and a plurality of unselected memory cell strings connected to an unselected second bit line.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: December 18, 2018
    Assignee: Samsung Electronics. Co., Ltd.
    Inventors: Doo-hyun Kim, Il-han Park, Jong-hoon Lee
  • Patent number: 10157489
    Abstract: The present invention relates to an ultrasound imaging system (10) comprising an ultrasound probe (20) having a transducer array (21) configured to provide an ultrasound receive signal. The system further comprises a B-mode volume processing unit (30) configured to generate a B-mode volume (31) based on the ultrasound receive signal, and a B-mode image processing unit (40) configured to provide a current B-mode image (41) based on the B-mode volume (31). The system further comprises a memory (50) configured to store a previously acquired 3D-vessel map (51). Also, the system comprises a registration unit (60) configured to register the previously acquired 3D-vessel map (51) to the B-mode volume (31) and to select a portion (61) of the 3D-vessel map corresponding to the current B-mode image (41). Further, the system comprises a display configured to display an ultrasound image (71) based on the current B-mode image (41) and the selected portion (61) of the 3D-vessel map (51).
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: December 18, 2018
    Assignee: Koninklijke Philips N.V.
    Inventors: Gary Cheng-How Ng, James Robertson Jago, Andrew Lee Robinson
  • Patent number: 10147496
    Abstract: At least one method, apparatus and system disclosed involves hard-coding data into an integrated circuit device. An integrated circuit device provided. Data for hard-wiring information into a portion of the integrated circuit device is received. A stress voltage signal is provided to a portion of a transistor of the integrated circuit device for causing a dielectric breakdown of the portion of the transistor for hard-wiring the data.
    Type: Grant
    Filed: January 26, 2018
    Date of Patent: December 4, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Akhilesh Gautam, Suresh Uppal, Min-hwa Chi
  • Patent number: 10143428
    Abstract: Provided is a method of providing location information regarding a location of a target object through a medical apparatus. The method includes setting photographing conditions about the target object, acquiring current location information of the target object, acquiring recommended location information of the target object according to the photographing conditions, outputting the acquired recommended location information, comparing the current location information with the recommended location information, and outputting additional information about a current location of the target object, according to a comparison result.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: December 4, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dong-jin Eun, Tae-kyun Kim
  • Patent number: 10147489
    Abstract: Provided herein may be a control circuit, peripheral circuit, semiconductor memory device and methods of operating the device and circuits. The method of operating a semiconductor memory device may include applying a control signal having a form, in which a step pulse is combined with a ramp signal, to a gate electrode of a transistor for setting up a voltage of a bit line of the selected memory cell. The method of operating a semiconductor memory device may include applying a program pulse to a word line of the selected memory cell.
    Type: Grant
    Filed: November 29, 2017
    Date of Patent: December 4, 2018
    Assignee: SK hynix Inc.
    Inventor: Da U Ni Kim
  • Patent number: 10146318
    Abstract: This disclosure provides a pose- or gesture-based recognition system that processes images of the human hand, downconverts degrees of freedom of the human hand to lower-dimensional space, and then maps the downconverted space to a character set. In one embodiment, the system is implemented in a smart phone or as a computer-input device that uses a virtual keyboard. As the user moves his or her hand, the smart phone or computer provides simulated vocal feedback, permitting the user to adjust hand position or motion to arrive at any desired character; this is particularly useful for embodiments which use a phonetic character set. Software that performs character selection can be implemented in a manner that is language/region agnostic, with a contextual dictionary being used to interpret a phonetic character set according to a specific language or region.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: December 4, 2018
    Inventor: Thomas Malzbender