Abstract: The present disclosure relates to a three-dimensional memory (3D) and a control method thereof. The 3D memory includes a first deck and a second deck which are stacked in a vertical direction of a substrate. The first deck and the second deck each includes a plurality of memory string. Each memory string includes a plurality of memory cells. The plurality of memory cells includes a first portion and a second portion. A diameter of channel structure corresponding to the first portion of memory cells is smaller than that of channel structure corresponding to the second portion of memory cells. The method includes performing a read operation for selected memory cells that are in at least one of the first deck or the second deck; and applying a pass voltage to non-selected memory cells other than the selected memory cells in the first deck and the second deck. A first pass voltage is lower than a second pass voltage.

Abstract: A semiconductor device may include first row lines each extending in a first direction, column lines each extending in a second direction crossing the first direction, second row lines each extending in the first direction, a plurality of first memory cells respectively coupled between the first row lines and the column lines, each of the plurality of first memory cells including a first variable resistance layer and a first dielectric layer positioned between the first variable resistance layer and a corresponding one of the first row lines, and a plurality of second memory cells respectively coupled between the second row lines and the column lines, each of the plurality of second memory cells including a second variable resistance layer and a second dielectric layer positioned between the second variable resistance layer and a corresponding one of the second row lines.

Abstract: A power supply circuit and a memory are provided. The power supply circuit includes a voltage source, multiple power supply circuits and a control circuit. The multiple power supply circuits are connected to the voltage source. If the voltage source is effective and the multiple power supply circuits are in an enable state, a voltage of a power supply terminal is pulled up to a preset voltage, and power is supplied to the load units during the pulling up process. A first-type power circuit enters the enable state if a first enable signal is received, and each of second-type power supply circuits enters the enable state if second enable signal is received.

Abstract: A variable resistive memory device includes a memory cell, a first current-applying block, a second current-applying block and a mode setting circuit. The memory cell includes a first electrode, a second electrode, and a memory layer, the memory layer interposed between the first electrode and the second electrode. The first current-applying block is configured to flow a first current to the first electrode that flows from the first electrode to the second electrode. The second current-applying block is configured to flow a second current to the second electrode that flows from the second electrode to the first electrode. The mode setting circuit is configured to selectively provide any one of the first electrode of the first current-applying block and the second electrode of the second current-applying block with a first voltage. When the memory cell is selected, the selected current-applying block, among the first current-applying block and the second current-applying block, is driven.

Abstract: An exemplary system, method, and computer-accessible medium for generating an image(s) of an anatomical structure(s) in a biological sample(s) can include receiving first wide field microscopy imaging information for the biological sample, generating second imaging information by applying a gradient-based distance transform to the first imaging information, and generating the image(s) based on the second imaging information. The second imaging information can be generated by applying an anisotropic diffusion procedure to the first imaging information. The second imaging information can be generated by applying a curvilinear filter and a Hessian-based enhancement filter after the application of the gradient-based distance transform. The second information can be generated by applying (i) a tube enhancement procedure or (ii) a plate enhancement procedure after the application of the gradient-based distance transform.

Abstract: In one aspect, a method for detecting terrain variations within a field includes receiving one or more images depicting an imaged portion of an agricultural field. The method also includes classifying a portion of the plurality of pixels that are associated with soil within the imaged portion of the agricultural field as soil pixels with each soil pixel being associated with a respective pixel height. Additionally, the method includes identifying each soil pixel having a pixel height that exceeds a height threshold as a candidate ridge pixel and each soil pixel having a pixel height that is less than a depth threshold as a candidate valley pixel. The method further includes determining whether a ridge or a valley is present within the imaged portion of the agricultural field based at least in part on the candidate ridge pixels or the candidate valley pixels.

Abstract: Existing currency validation (CVAL) devices, systems, and methods are too slow, costly, intrusive, and/or bulky to be routinely used in common transaction locations (e.g., at checkout, at an automatic teller machine, etc.). Presented herein are devices, systems, and methods to facilitate optical validation of documents, merchandise, or currency at common transaction locations and to do so in an obtrusive and convenient way. More specifically, the present invention embraces a validation device that may be used alone or integrated within a larger system (e.g., point of sale system, kiosk, etc.). The present invention also embraces methods for currency validation using the validation device, as well as methods for improving the quality and consistency of data captured by the validation device for validation.

Abstract: The present invention relates to the field of digital memory, and in particular to a multiple-time programmable (MTP) memory employing error correction codes (ECC), the MTP memory being made up of one-time programmable (OTP) memory modules. Pointers to the memory address of currently in-use OTP memory blocks in use for each virtual MTP memory block are stored in OTP memory with an error correcting code. The pointers encode the memory addresses according to a scheme that ensure that only bit changes in a single direction are required in both the pointer data and the error correction code when the memory address is incremented.

Abstract: A method for determining a localization pose of an at least partially automated mobile platform, the mobile platform being equipped to generate ground images of an area surrounding the mobile platform, and being equipped to receive aerial images of the area surrounding the mobile platform from an aerial-image system. The method includes: providing a digital ground image of the area surrounding the mobile platform; receiving an aerial image of the area surrounding the mobile platform; generating the localization pose of the mobile platform with the aid of a trained convolutional neural network, which has a first trained encoder convolutional-neural-network part and a second trained encoder convolutional-neural-network part.

Abstract: A memory device is provided. The memory device includes several sense amplifiers and at least one reference cell. Each of the sense amplifiers has a first terminal and a second terminal. The first terminals of the sense amplifiers are coupled to a memory cell block, and the second terminals of the sense amplifiers are coupled together to transmit a read current. The at least one reference cell transmits the read current to a ground terminal. The at least one reference cell has a decreased resistance value when a number N of the sense amplifiers increases.

Abstract: A method for operating a memory is disclosed. The memory includes a first group of word lines, a second group of word lines, a first dummy word line, and a second dummy word line. The first dummy word line and the second dummy word line are between the first group of word lines and the second group of word lines. A first pass voltage is applied to the first dummy word line and applying a second pass voltage to the second dummy word line. A program voltage is applied to a selected word line, wherein a condition is met: a first voltage difference between the first pass voltage and a first threshold voltage of a first dummy cell corresponding to the first dummy word line is different from a second voltage difference between the second pass voltage and a second threshold voltage of a second dummy cell corresponding to the second dummy word line.

Abstract: Methods, systems, and devices for parallel drift cancellation are described. In some instances, during a first duration, a first voltage may be applied to a word line to threshold one or more memory cells included in a first subset of memory cells. During a second duration, a second voltage may be applied to the word line to write a first logic state to one or more memory cells included in the first subset and to threshold one or more memory cells included in a second subset of memory cells. During a third duration, a third voltage may be applied to the word line to write a second logic state to one or more memory cells included in the second subset of memory cells.

Abstract: Disclosed are systems and methods involving memory-side write training to improve data valid window. In one implementation, a method for performing memory-side write training may comprise delaying a rising edge or a falling edge of a first data signal, delaying a rising edge or a falling edge of a second data signal, and aligning the two adjusted signals to reduce a window of time that the data signals are not valid and thereby improve or optimize the data valid window (DVW) of a memory array. According to implementations herein, various edges of data signals and clock signals may be adjusted or delayed via dedicated trim cells or circuitry present in the data paths located on the memory side of a system.

Abstract: The disclosure extends to methods, systems, and apparatuses for automated fixation generation and more particularly relates to generation of synthetic saliency maps. A method for generating saliency information includes receiving a first image and an indication of one or more sub-regions within the first image corresponding to one or more objects of interest. The method includes generating and storing a label image by creating an intermediate image having one or more random points. The random points have a first color in regions corresponding to the sub-regions and a remainder of the intermediate image having a second color. Generating and storing the label image further includes applying a Gaussian blur to the intermediate image.

Abstract: Multilevel command and address (CA) signals are used to provide commands and memory addresses from a controller to a memory system. Using multilevel signals CA signals may allow for using fewer signals compared to binary signals to represent a same number of commands and/or address space, or using a same number of multilevel CA signals to represent a larger number of commands and/or address space. A number of external command/address terminals may be reduced without reducing a set of commands and/or address space. Alternatively, a number of external terminals may be maintained, but provide for an expanded set of commands and/or address space.

Abstract: Disclosed is a method for analyzing a distribution of retinal lesions in a mouse model, including: scanning a mouse posterior polar fundus based on optical coherence tomography (OCT), and acquiring lesion images of the mouse posterior polar fundus; acquiring lesion distribution coordinates based on the lesion images of the mouse posterior polar fundus; constructing a coordinate map of a lesion distribution rule based on the lesion distribution coordinates; and acquiring lesion distribution in quadrants based on the coordinate map of the lesion distribution rule, and calculating and counting a number of lesions in each quadrant.

Abstract: A method of correcting bias temperature instability in memory arrays may include applying a first bias to a memory cell, where the memory cell may include a memory element and a select element, and the first bias may causes a value to be stored in the memory element. The first bias causes a bias temperature instability (BTI) associated with the memory cell to increase. The method may also include applying a second bias to the memory cell, where the second bias may have a polarity that is opposite of the first bias, and the value stored in the memory element remains in the memory element after the second bias is applied. The second bias may also cause the BTI associated with the memory cell to decrease while maintaining any value stored in the memory cell.

Abstract: Memory devices have an array of elements in two or more dimensions. The memory devices use multiple access lines arranged in a grid to access the memory devices. Memory cells are located at intersections of the access lines in the grid. Drivers are used for each access line and configured to transmit a corresponding signal to respective memory cells of the plurality of memory cells via a corresponding access line. The memory devices also include compensation circuitry configured to determine which driving access lines driving a target memory cell of the plurality of memory cells has the most distance between the target memory cell and a respective driver. The plurality of access lines comprise the driving access lines. The compensation circuitry also is configured to output compensation values to adjust the voltages of the driving access lines based on a polarity of the voltage of the longer driving access line.

Abstract: A system may be configured to collect geospatial features (in vector form) such that a software application is operable to edit an object represented by at least one vector. Some embodiments may: generate, via a trained machine learning model, a pixel map based on an aerial or satellite image; convert the pixel map into vector form; and store the vectors. This conversion may include a raster phase and a vector phase. A system may be configured to obtain another image, generate another pixel map based on the other image, convert the other pixel map into vector form, and compare the vectors to identify changes between the images. Some implementations may cause identification, based on a similarity with converted vectors, of a more trustworthy set of vectors for subsequent data source conflation.

Abstract: The present disclosure relates to a memory device comprising a plurality of memory cells, each memory cell being programmable to a logic state corresponding to a threshold voltage exhibited by the memory cell in response to an applied voltage, and a logic circuit portion operatively coupled to the plurality of memory cells, wherein the logic circuit portion is configured to scan memory addresses of the memory device, and to generate seasoning pulses to be applied to the addressed pages of the memory device. A related electronic system and related methods are also disclosed.