Patents Examined by W. David Coleman
  • Patent number: 10147797
    Abstract: A silicon carbide semiconductor device, including a silicon carbide semiconductor structure, an insulated gate structure, an interlayer insulating film formed on the insulated gate structure, a poly-silicon film formed on the interlayer insulating film, and a main electrode formed on the poly-silicon film and in electrical connection with the silicon carbide semiconductor structure. The insulated gate structure includes a gate insulating film, which is a silicon dioxide film contacting the silicon carbide semiconductor structure, and a gate electrode formed on the gate insulating film.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: December 4, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takumi Fujimoto, Naoki Kumagai
  • Patent number: 9726631
    Abstract: An exemplary biosensor sensor for detecting the presence of a biological material includes an SOI substrate, a BJT formed on at least a portion of the substrate, and a sensing structure formed on at least a portion of an upper surface of the BJT. The BJT includes an emitter region, a collector region and a self-aligned epitaxially grown intrinsic base region laterally adjacent to the emitter and collector regions. The sensing structure includes an opening, centered above and exposing the intrinsic base region, and at least one dielectric layer formed in the opening and contacting at least a portion of the intrinsic base region. The dielectric layer is configured to respond to charges in biological molecules.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: August 8, 2017
    Assignee: International Business Machines Corporation
    Inventors: Jin Cai, Tak H. Ning, Jeng-Bang Yau, Sufi Zafar
  • Patent number: 9711400
    Abstract: Interconnect structures are provided that include an intermetallic compound as either a cap or liner material. The intermetallic compound is a thermal reaction product of a metal or metal alloy of an interconnect metallic region with a metal of either a metal cap or a metal layer. In some embodiments, the metal cap may include a metal nitride and thus a nitride-containing intermetallic compound can be formed. The formation of the intermetallic compound can improve the electromigration resistance of the interconnect structures and widen the process window for fabricating interconnect structures.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: July 18, 2017
    Assignee: International Business Machines Corporation
    Inventor: Chih-Chao Yang
  • Patent number: 8247855
    Abstract: A ferroelectric device employs ferroelectric electrodes as local interconnect(s). One or more circuit features are formed within or on a semiconductor body. A first dielectric layer is formed over the semiconductor body. Lower contacts are formed within the first dielectric layer. A bottom electrode is formed over the first dielectric layer and on the lower contacts. A ferroelectric layer is formed on the bottom electrode. A top electrode is formed on the ferroelectric layer. A second dielectric layer is formed over the first dielectric layer. Upper contacts are formed within the second dielectric layer and in contact with the top electrode. Conductive features are formed on the upper contacts.
    Type: Grant
    Filed: September 12, 2006
    Date of Patent: August 21, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Scott R. Summerfelt
  • Patent number: 8124497
    Abstract: A method of manufacturing a nitride semiconductor device is disclosed. The method includes forming a gallium nitride (GaN) epitaxial layer on a first support substrate, forming a second support substrate on the GaN epitaxial layer, forming a passivation layer on a surface of the other region except for the first support substrate, etching the first support substrate by using the passivation layer as a mask, and removing the passivation layer and thereby exposing the second support substrate and the GaN epitaxial layer.
    Type: Grant
    Filed: November 29, 2010
    Date of Patent: February 28, 2012
    Assignee: Siltron, Inc.
    Inventors: Yong-Jin Kim, Dong-Kun Lee, Doo-Soo Kim, Ho-Jun Lee, Kye-Jin Lee
  • Patent number: 8084280
    Abstract: A method of manufacturing a solar cell wherein a pre-cleaning step is completed prior to a saw damage removal step and prior to texturization, thereby resulting in the subsequently formed textured surface to have a more homogeneous textural morphology.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: December 27, 2011
    Inventors: Ismail Kashkoush, Gim-Syang Chen
  • Patent number: 8067305
    Abstract: Provided are methods for forming an electrically conductive structure of a desired three-dimensional shape on a substantially planar surface of a substrate, e.g., a semiconductor wafer. Typically, the particulate matter is deposited in a layer-by-layer manner and adhered to selected regions on the substrate surface. The particulate matter may be deposited to produce a mold for forming the structure and/or to produce the structure itself. A three-dimensional printer with associated electronic data may be used without the need of a lithographic mask or reticle.
    Type: Grant
    Filed: September 3, 2008
    Date of Patent: November 29, 2011
    Assignee: Ultratech, Inc.
    Inventors: Arthur W. Zafiropoulo, Andrew M. Hawryluk
  • Patent number: 8058089
    Abstract: Electromechanical circuits, such as memory cells, and methods for making same are disclosed. The circuits include a structure having electrically conductive traces and supports extending from a surface of the substrate, and nanotube ribbons suspended by the supports that cross the electrically conductive traces, wherein each ribbon comprises one or more nanotubes. The electro-mechanical circuit elements are made by providing a structure having electrically conductive traces and supports, in which the supports extend from a surface of the substrate. A layer of nanotubes is provided over the supports, and portions of the layer of nanotubes are selectively removed to form ribbons of nanotubes that cross the electrically conductive traces. Each ribbon includes one or more nanotubes.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: November 15, 2011
    Assignee: Nantero Inc.
    Inventors: Brent M. Segal, Darren K. Brock, Thomas Rueckes
  • Patent number: 8026560
    Abstract: Techniques for ultra-sensitive detection are provided. In one aspect, a detection device is provided. The detection device comprises a source; a drain; a nanowire comprising a semiconductor material having a first end clamped to the source and a second end clamped to the drain and suspended freely therebetween; and a gate in close proximity to the nanowire.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: September 27, 2011
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Ardakani, Sudhir Gowda, Supratik Guha, Hendrik F. Hamann, Emanuel Tutuc
  • Patent number: 8026159
    Abstract: A method of manufacturing a semiconductor device includes the steps of loading a substrate into a processing chamber; processing the substrate by supplying plural kinds of reaction substances into the processing chamber multiple number of times; and unloading the processed substrate from the processing chamber, wherein at least one of the plural kinds of reaction substances contains a source gas obtained by vaporizing a liquid source by a vaporizing part; in the step of processing the substrate, vaporizing operation of supplying the liquid source to the vaporizing part and vaporizing the liquid source is intermittently performed, and at least at a time other than performing the vaporizing operation of the liquid source, a solvent capable of dissolving the liquid source is flown to the vaporizing part at a first flow rate; and at a time other than performing the vaporizing operation of the liquid source and every time performing the vaporizing operation of the liquid source prescribed number of times, the solv
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: September 27, 2011
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Sadayoshi Horii, Yoshinori Imai
  • Patent number: 8022423
    Abstract: An (Al, Ga, In)N light emitting diode (LED) in which multi-directional light can be extracted from one or more surfaces of the LED before entering a shaped optical element and subsequently being extracted to air. In particular, the (Al, Ga, In)N and transparent contact layers (such as ITO or ZnO) are embedded in or combined with a shaped optical element comprising an epoxy, glass, silicon or other material molded into an inverted cone shape, wherein most of the light entering the inverted cone shape lies within a critical angle and is extracted. In addition, the present invention stands the LED on end, i.e., rotates the position of the LED within the shaped optical element by approximately 90° as compared to a conventional LED, in order to extract light more effectively from the LED.
    Type: Grant
    Filed: March 3, 2010
    Date of Patent: September 20, 2011
    Assignee: The Regents of the University of California
    Inventors: Shuji Nakamura, Steven P. DenBaars
  • Patent number: 8017506
    Abstract: A thin film transistor device reduced substantially in resistance between the source and the drain by incorporating a silicide film, which is fabricated by a process comprising forming a gate insulator film and a gate contact on a silicon substrate, anodically oxidizing the gate contact, covering an exposed surface of the silicon semiconductor with a metal and irradiating an intense light such as a laser beam to the metal film either from the upper side or from an insulator substrate side to allow the metal coating to react with silicon to obtain a silicide film. The metal silicide layer may be obtained otherwise by tightly adhering a metal coating to the exposed source and drain regions using an insulator formed into an approximately triangular shape, preferably 1 ?m or less in width, and allowing the metal to react with silicon.
    Type: Grant
    Filed: October 23, 2009
    Date of Patent: September 13, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yasuhiko Takemura, Hongyong Zhang, Satoshi Teramoto
  • Patent number: 8013445
    Abstract: A semiconductor contact structure includes a copper plug formed within a dual damascene, single damascene or other opening formed in a dielectric material and includes a composite barrier layer between the copper plug and the sidewalls and bottom of the opening. The composite barrier layer preferably includes an ALD TaN layer disposed on the bottom and along the sides of the opening although other suitable ALD layers may be used. A barrier material is disposed between the copper plug and the ALD layer. The barrier layer may be a Mn-based barrier layer, a Cr-based barrier layer, a V-based barrier layer, a Nb-based barrier layer, a Ti-based barrier layer, or other suitable barrier layers.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: September 6, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiang-Huan Lee, Ming Han Lee, Ming-Shih Yeh, Chen-Hua Yu
  • Patent number: 8013400
    Abstract: A method for scaling channel length in a semiconductor device is provided. The method includes increasing a pitch to reduce a development inspection critical dimension (DICD) for a plurality of polysilicon lines. The polysilicon lines are trimmed to provide a reduced-size channel length, based on the reduced DICD, for each polysilicon line. For a particular embodiment, the semiconductor device is fabricated using a photolithography tool having a wavelength of 248 nm, the pitch is about 800 nm, and the reduced-size channel length is about 0.11 ?m.
    Type: Grant
    Filed: April 21, 2008
    Date of Patent: September 6, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Li-Heng Chou, Jiankang Bu
  • Patent number: 8008659
    Abstract: A substrate bias is controlled such that a leakage current is minimum. A semiconductor integrated circuit device comprises a leakage detecting circuit which detects a leakage current by using leakage detecting MOSFETs, a control circuit which generates a control signal depending on an output from the leakage detecting circuit, a substrate bias generating circuit which changes a substrate bias depending on the control signal, and a controlled circuit including a MOSFET having the same characteristics as that of each of the leakage detecting MOSFETs. The leakage detecting circuit detects a substrate leakage current which includes as the substrate bias becomes deep and a subthreshold leakage current which decreases as the substrate bias becomes deep.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: August 30, 2011
    Assignee: NEC Corporation
    Inventors: Yoshifumi Ikenaga, Koichi Takeda, Masahiro Nomura
  • Patent number: 8008160
    Abstract: A method of forming a trench device structure having a single-side buried strap is provided. The method includes forming a deep trench in a semiconductor substrate, said deep trench having a first side portion and a second side portion; depositing a node dielectric on said deep trench, wherein said node dielectric covers said first side portion and said second side portion; depositing a first conductive layer over said node dielectric; performing an ion implantation or ion bombardment at an angle into a portion of said node dielectric, thereby removing said portion of said node dielectric from said first side portion of said deep trench; and depositing a second conductive layer over said first conductive layer, wherein said second conductive layer outdiffuses into a portion of said semiconductor substrate. A trench device structure having a single-side buried strap is also provided.
    Type: Grant
    Filed: January 21, 2008
    Date of Patent: August 30, 2011
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Xi Li, Richard Wise
  • Patent number: 8003410
    Abstract: A method of operating a quantum system comprising computational elements, including an insulated ring of superconductive material, and semi-closed rings used as an interface between the computational elements and the external world, is disclosed. In one aspect, the method comprises providing an electrical signal, e.g. a current, in an input ring magnetically coupled to a computational element, which generates a magnetic field in the computational element and sensing the change in the current and/or voltage of an output element magnetically coupled to the computational element. The electrical input signal can be an AC signal or a DC signal. The computational element is electromagnetically coupled with other adjacent computational elements and/or with the interface elements. The corresponding magnetic flux between the computational elements and/or the interface elements acts as an information carrier. Ferromagnetic cores are used to improve the magnetic coupling between adjacent elements.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: August 23, 2011
    Assignees: IMEC, Katholieke Universiteit Leuven
    Inventors: Christoph Kerner, Wim Magnus, Dusan Golubovic
  • Patent number: 7998845
    Abstract: To provide a semiconductor device in which a semiconductor film having a leveled main surface is used as an active layer. A semiconductor film (5) having the leveled main surface with an rms of less than 10 nm and a P-V value of less than 70 nm which each indicate a surface roughness is formed by crystallizing a silicon film (3) containing germanium in a concentration of several %, preferably 0.1 to 10 atoms % and irradiating the film with a laser light. In a case of performing a crystallization by use of a metal element for accelerating the crystallization. The semiconductor film high in an orientation rate of the crystal as well as in levelness is obtained.
    Type: Grant
    Filed: April 19, 2007
    Date of Patent: August 16, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kenji Kasahara, Shunpei Yamazaki
  • Patent number: 7998820
    Abstract: A device and method of formation are provided for a high-k gate dielectric and gate electrode. The high-k dielectric material is formed, and a silicon-rich film is formed over the high-k dielectric material. The silicon-rich film is then treated through either oxidation or nitridation to reduce the Fermi-level pinning that results from both the bonding of the high-k material to the subsequent gate conductor and also from a lack of oxygen along the interface of the high-k dielectric material and the gate conductor. A conductive material is then formed over the film through a controlled process to create the gate conductor.
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: August 16, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Liang-Gi Yao
  • Patent number: 7994536
    Abstract: An integrated circuit includes a U-shaped access device and a first line coupled to a first side of the access device. The integrated circuit includes a contact coupled to a second side of the access device and self-aligned dielectric material isolating the first line from the contact.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: August 9, 2011
    Assignee: Qimonda AG
    Inventors: Rolf Weis, Thomas Happ