Abstract: This method for producing a non-planar microelectronic component, especially a concave component, involves superposing a layer that contains an active flexible circuit above a cavity shaped according to the desired profile of said component, said cavity being formed in substrate; and applying a pressure difference either side of said layer thereby causing slumping of the flexible circuit into the cavity therefore causing the circuit to assume the shape of the cavity. Superposition of the flexible circuit and the cavity is realized by filling the cavity with a material capable of being selectively removed relative to the substrate and the flexible circuit; then fitting or forming the flexible circuit on the cavity thus filled; then forming at least one feedthrough to access the filled cavity; and by selectively etching the material that fills the cavity via at least one feedthrough in order to remove said material.

Abstract: A method for protecting a circuit from a high energy pulse includes placing a PPTC resistive element in series with the circuit and placing an energy pulse clamping semiconductor diode in shunt across the circuit and further includes forming the diode to have: a substrate with carriers of a first type of conductivity in a first, high concentration level (e.g. n++), a first major face and a second major face opposite to the first major face; a layer of semiconductor material having carriers of the first type of conductivity in a second concentration level lower than the first level (e.g. n+), and an outer surface; a region formed at an outer surface having carriers of a second type of conductivity in a third concentration level (e.g. p+); at least one cell having carriers of the second type of conductivity in a fourth concentration level greater than the third concentration level (e.g. p++); and, a cathode electrode and an anode electrode.

Abstract: This invention provides methods and systems, e.g., to control the flow of photo-polymerizable resins. In the method, e.g., flow of a photo-polymerizable resin is restricted from illuminated resin exclusion regions on a substrate surface by precisely situated flow barriers. A system to control photo-polymerizable resin flow includes, e.g., a light source, a mask and a substrate.

Abstract: Disclosed are a light emitting device and a method for manufacturing the same. A light emitting diode comprises a plurality of Un-GaN layers and a plurality of N-type semiconductor layers, an active layer on the N-type semiconductor layer, and a P-type semiconductor layer on the active layer, wherein at least two of the Un-GaN layers and at least two of the N-type semiconductor layers are alternatively stacked on each other.

Abstract: The present invention relates to an apparatus (10) for aligning an optical device with an object. The apparatus comprises, a frame (12), a support unit (16) for supporting said optical device or said object and a transportation device (14) arranged to at least tilt the support unit in relation to the frame, wherein a segment of a sphere (18, 22) is provided, which segment defines a spherical surface (20), and the tilting movement of the support unit is controlled by said spherical surface. The apparatus according to the invention allows for a tilting movement between said optical device and said object, while such movement does not lead to a shift in focus. Furthermore the invention relates to an optical instrument and a semiconductor process system comprising said apparatus.

Abstract: The invention relates to an organic electronic component, such as e.g. an organic light diode or an organic solar cell with structures made of passivation material, the passivation material comprising at least one dessicant.

Abstract: An integrated circuit includes a device stack including: a memory device with a first wireless coupling element, and a semiconductor device with a second wireless coupling element. The first and second wireless coupling elements are arranged face-to-face and are configured to provide a wireless connection between the memory device and the semiconductor device.

Abstract: There is a process for reducing the sheet resistance of phosphorus-implanted poly-silicon. In an example embodiment, there is an MOS transistor structure. The structure has a gate region, drain region and a source region. A method for reducing the sheet resistance of the gate region comprises depositing intrinsic amorphous silicon at a predetermined temperature onto the gate region. An amorphizing species is implanted into the intrinsic amorphous silicon. Phosphorus species are then implanted into the gate region of the MOS transistor structure. A feature of this embodiment includes using Ar+ as the amorphizing species.

Abstract: The contrast offered by a spatial light modulator device may be enhanced by positioning nonreflective elements such as supporting posts and moveable hinges, behind the reflecting surface of the pixel. In accordance with one embodiment, the reflecting surface is suspended over and underlying hinge-containing layer by integral ribs of the reflecting material defined by gaps in a sacrificial layer. In accordance with an alternative embodiment, the reflecting surface is separated from the underlying hinge by a gap formed in an intervening layer, such as oxide. In either embodiment, walls separating adjacent pixel regions may be recessed beneath the reflecting surface to further reduce unwanted scattering of incident light and thereby enhance contrast.

Abstract: It is an object of the present invention to provide a semiconductor device in which an arrangement area of capacitance can be reduced and resonance frequency can be easily adjusted. The semiconductor device includes an antenna and a resonance circuit including a capacitor connected to the antenna in parallel where the capacitor is formed by connecting x pieces of first capacitor (x is an arbitrary natural number), y pieces of second capacitor (y is an arbitrary natural number), and z pieces of third capacitor (z is an arbitrary natural number) in parallel; and the first capacitor, the second capacitor, and the third capacitor have different capacitance values from each other. It is preferable that each of the first capacitor, the second capacitor, and the third capacitor be a MIS capacitor. Further, at least one of the first capacitor, the second capacitor, and the third capacitor is preferably formed by connecting a plurality of capacitors in parallel.

Abstract: A MOSFET with an isolation structure is provided. An N-type MOSFET includes a first N-type buried layer and a P-type epitaxial layer disposed in a P-type substrate. A P-type FET includes a second N-type buried layer and the P-type epitaxial layer disposed in the P-type substrate. The first, second N-type buried layers and the P-type epitaxial layer provide isolation between FETs. In addition, a plurality of separated P-type regions disposed in the P-type epitaxial layer further provides an isolation effect. A first gap exists between a first thick field oxide layer and a first P-type region, for raising a breakdown voltage of the N-type FET. A second gap exists between a second thick field oxide layer and a second N-well, for raising a breakdown voltage of the P-type FET.

Abstract: A method for bonding a semiconductor structure with a substrate and a high efficiency photonic device manufactured by using the same method are disclosed. The method comprises steps of: providing a semiconductor structure and a substrate; forming a composite bonding layer on the semiconductor structure; and bonding the substrate with the composite bonding layer on the semiconductor structure to form a composite alloyed bonding layer. The semiconductor structure includes a compound semiconductor substrate and a high efficiency photonic device is produced after the compound semiconductor substrate is removed. Besides, the composite bonding layer can be formed on the substrate or formed on both the semiconductor structure and substrate simultaneously.

Abstract: The concentration of oxygen, which causes problems such as decreases in brightness and dark spots through degradation of electrode materials, is lowered in an organic light emitting element having a layer made from an organic compound between a cathode and an anode, and in a light emitting device structured using the organic light emitting element. The average concentration of impurities contained in a layer made from an organic compound used in older to form an organic light emitting element having layers such as a hole injecting layer, a hole transporting layer, a light emitting layer, an electron transporting layer, and an electron injecting layer, is reduced to 5×1019/cm2 or less, preferably equal to or less than 1×1019/cm2, by removing the impurities with the present invention. Formation apparatuses are structured as stated in the specification in order to reduce the impurities in the organic compounds forming the organic light emitting elements.

Abstract: A method for introducing one or more impurities into nano-structured materials. The method includes providing a nanostructured material having a feature size of about 100 nm and less. The method includes subjecting a surface region of the nanostructured material to one or more impurities to form a first region having a first impurity concentration within a vicinity of the surface region. In a specific embodiment, the method includes applying a driving force to one or more portions of at least the nanostructured material to cause the first region to form a second region having a second impurity concentration.

Abstract: The invention relates to a jig for producing capacitor elements, which is formed of resin material and is used for accommodate a plurality of capacitor element substrates therein to thereby batch-process the substrates. The jig is characterized in that portions of the jig at which the jig is supported during the process are protected with metal material. According to the invention, a group of capacitors each having a semiconductor layer serving as one electrode can be simultaneously produced with narrow variety in capacitance and with good precision, repeatedly, by using the jig having a high durability.

Abstract: A bulk-doped semiconductor that is at least one of the following: a single crystal, an elongated and bulk-doped semiconductor that, at any point along its longitudinal axis, has a largest cross-sectional dimension less than 500 nanometers, and a free-standing and bulk-doped semiconductor with at least one portion having a smallest width of less than 500 nanometers. At least one portion of such a semiconductor may a smallest width of less than 200 nanometers, or less than 150 nanometers, or less than 100 nanometers, or less than 80 nanometers, or less than 70 nanometers, or less than 60 nanometers, or less than 40 nanometers, or less than 20 nanometers, or less than 10 nanometers, or even less than 5 nanometers. Such a semiconductor may be doped during growth. Such a semiconductor may be part of a device, which may include any of a variety of devices and combinations thereof, and a variety of assembling techniques may be used to fabricate devices from such a semiconductor.

Abstract: Method of fabricating a thin-film transistor (TFT) in which a gate metal is deposited onto a substrate in order to form the gate of the thin-film transistor. The substrate may be an insulative substrate or a color filter. In a first method, the gate metal is subjected to an H2 plasma. After subjecting the gate metal to an H2 plasma, the gate insulating film is deposited onto the gate. In a second method, first and second layers of gate insulating film are respectively deposited on the gate at a first and second deposition rates. One layer is deposited under H2 or argon dilution conditions and has improved insulating conditions while the other layer serves to lower the overall compressive stress of the dual layer gate insulator. In a third method, an n+ silicon film is formed on a substrate by maintaining a flow of silane, phosphine and hydrogen gas into a processing chamber at substrate temperatures of about 300° C. or less.

Abstract: Double patterning techniques and structures are generally described. In one example, a method includes depositing a first photoresist to a semiconductor substrate, forming a first integrated circuit (IC) pattern in the first photoresist, the first IC pattern comprising one or more trench structures, protecting the first IC pattern in the first photoresist from actions that form a second IC pattern in a second photoresist, depositing the second photoresist to the first IC pattern, and forming the second IC pattern in the second photoresist, the second IC pattern comprising one or more structures that are sufficiently close to the one or more trench structures of the first IC pattern to cause scumming of the second photoresist in the one or more trench structures of the first IC pattern.

Abstract: A method for fabricating a semiconductor device may include: forming an outer trench, including: a first trench, and a second trench formed under the first trench, the second trench being formed by etching a substrate, forming a dielectric layer, which fills the second trench, by performing a thermal oxidation process, such that a width of the second trench is less than a width of the first trench, forming a gate dielectric layer along a surface of a semiconductor structure including the dielectric layer, and forming a gate electrode, which fills a remaining portion of the outer trench, over the gate dielectric layer.

Abstract: An embodiment of a process is disclosed herein for fabricating a memory device integrated on a semiconductor substrate and comprising at least a nanocrystal memory cell and CMOS transistors respectively formed in a memory area and in a circuitry area. According to an embodiment, a process includes forming a nitride layer having an initial thickness, placed above a nanocrystal layer, in the memory area and the formation in the circuitry area of at least one submicron gate oxide. The process also provides that the initial thickness is such as to allow a complete transformation of the nitride layer into an oxide layer at upon formation of said at least one submicron gate oxide.