Abstract: A method of planarizing a dielectric insulating layer including providing a substrate including forming a first dielectric insulating layer having a concave and convex portion on the substrate; forming an organic resinous layer on the first dielectric insulating layer and exposing the convex portion of the first dielectric insulating layer; isotropically etching the first dielectric insulating layer convex portion; removing the organic resinous layer; and, forming a second dielectric insulating layer on the first dielectric insulating layer.

Abstract: Disclosed herein are embodiments of electronic package incorporating a thermal interface material (e.g., a metal TIM) that is positioned between a lid and a chip on a substrate. The TIM has a predetermined (i.e., repeatable) minimum thickness and is further registered to the top surface of the chip (i.e., the TIM has an essentially symmetric shape and does not extend vertically along the sidewalls of the chip). Also, disclosed herein are embodiments of a method of forming such an electronic package that uses a hierarchical heating process that cures a lid sealant, thereby securing the lid to the substrate, and then reflows (i.e., melts and cools) the TIM, thereby adhering the TIM to both the chip and lid. This hierarchical heating process ensures that the TIM has the above-mentioned characteristics (i.e., a predetermined minimum thickness and registration to the top surface of the chip) and further provides robust process windows for high-yield, low-cost electronic package manufacturing.

Abstract: Disclosed are a semiconductor structure and a method that allow for simultaneous voltage/current conditioning of multiple memory elements in a nonvolatile memory device with multiple memory cells. The structure and method incorporate the use of a resistor connected in series with the memory elements to limit current passing through the memory elements. Specifically, the method and structure incorporate a blanket temporary series resistor on the wafer surface above the memory cells and/or permanent series resistors within the memory cells. During the conditioning process, these resistors protect the transition metal oxide in the individual memory elements from damage (i.e., burn-out), once it has been conditioned.

Abstract: A method of forming a magnetoelectronic device includes forming a dielectric material (114) surrounding a magnetic bit (112), etching the dielectric material (114) to define an opening (122) over the magnetic bit (112) without exposing the magnetic bit (112), the opening (122) having a sidewall, depositing a blanket layer (132) of cladding material over the dielectric material (118), including over the sidewall, removing by a sputtering process the blanket layer (132) in the bottom of the opening (122) and the dielectric material (124) over the magnetic bit (112), and forming a conductive material (146) within the opening (122) to form a bit line (154). This process reduces errors caused by process irregularities such as edges of the bits (112) protruding and thereby causing defects in the cladding layer (132) formed thereover.

Abstract: Methods for forming a photovoltaic cell electrode structure, wherein the photovoltaic cell includes a semiconductor substrate having a passivation layer thereon, includes providing a plurality of contact openings through the passivation layer to the semiconductor substrate, selectively plating a contact metal into the plurality of contact openings to deposit the contact metal, depositing a metal containing material on the deposited contact metal, and firing the deposited contact metal and the deposited metal containing material. The metal containing material may include a paste containing a silver or silver alloy along with a glass frit and is substantially free to completely free of lead. The methods may also use light activation of the passivation layer or use seed layers to assist in the plating.

Abstract: A method is provided for forming doped hafnium zirconium based films by atomic layer deposition (ALD) or plasma enhanced ALD (PEALD). The method includes disposing a substrate in a process chamber and exposing the substrate to a gas pulse containing a hafnium precursor, a gas pulse containing a zirconium precursor, and a gas pulse containing one or more dopant elements. The dopant elements may be selected from Group II, Group XIII, silicon, and rare earth elements of the Periodic Table. Sequentially after each precursor and dopant gas pulse, the substrate is exposed to a gas pulse containing an oxygen-containing gas, a nitrogen-containing gas, or an oxygen- and nitrogen-containing gas. In alternative embodiments, the hafnium and zirconium precursors may be pulsed together, and either or both may be pulsed with the dopant elements. The sequential exposing steps may be repeated to deposit a doped hafnium zirconium based film with a predetermined thickness.

Abstract: Provided is a method of semiconductor fabrication including process steps allowing for defining and/or modifying a gate structure height during the fabrication process. The gate structure height may be modified (e.g., decreased) at one or more stages during the fabrication by etching a portion of a polysilicon layer included in the gate structure. The method includes forming a coating layer on the substrate and overlying the gate structure. The coating layer is etched back to expose a portion of the gate structure. The gate structure (e.g., polysilicon) is etched back to decrease the height of the gate structure.

Abstract: The present invention provides a display device and a manufacturing method thereof. The display device includes a gate line, a data line that is insulated from and crosses the gate line, a thin film transistor including a semiconductor layer and connected to the gate line and the data line, a pixel electrode connected to the thin film transistor, and a dummy drain electrode adjacent to a channel region of the thin film transistor. The dummy drain electrode is not connected to the pixel electrode.

Abstract: A precursor gas mixture for depositing an epitaxial carbon-doped silicon film is described. The precursor gas mixture is comprised of a volume of a silicon precursor gas, a volume of acetylene gas and a volume of a carrier gas. A method of forming a semiconductor structure having an epitaxial carbon-doped silicon film is also described. In the method, a substrate having a high polarity dielectric region and a low polarity crystalline region is provided. A precursor gas is flowed to provide a silyl surface above the high polarity dielectric region and a carbon-doped silicon layer above the low polarity crystalline region. The silyl surface is then removed from above the high polarity dielectric region. The flowing and removing steps are repeated to provide a carbon-doped silicon film of a desired thickness above the low polarity crystalline region.

Abstract: To improve bonding strength and improve reliability of an SOI substrate in bonding a semiconductor substrate and a base substrate to each other even when an insulating film containing nitrogen is used as a bonding layer, an oxide film is provided on the semiconductor substrate side, a nitrogen-containing layer is provided on the base substrate side, and the oxide film formed on the semiconductor substrate and the nitrogen-containing layer formed over the base substrate are bonded to each other. Further, plasma treatment is performed on at least one of the oxide film and the nitrogen-containing layer before bonding the oxide film formed on the semiconductor substrate and the nitrogen-containing layer formed over the base substrate to each other. Plasma treatment can be performed in a state in which a bias voltage is applied.

Abstract: Some embodiments include methods of forming openings in which a metal-containing structure is formed over a region of a semiconductor substrate. A patterned metal-containing material is formed over the metal-containing structure, with the metal-containing material having a gap extending therethrough. An entirety of the metal-containing structure is removed through the gap to leave an opening over the region of the semiconductor substrate. The region of the semiconductor substrate may comprise CMOS sensors, and one or both of filter material and microlens material may be formed within the opening.

Abstract: A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. The metal vias are surrounded by organic material. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. The RDL and THV provide expanded interconnect flexibility to adjacent die. Repassivation layers are formed between the RDL on the second surface of the die for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The RDL provide electrical interconnect to the adjacent die. Bond wires and solder bumps also provide electrical connection to the semiconductor die.

Abstract: To provide a method for manufacturing an SOI substrate having a single crystal semiconductor layer having a small and uniform thickness over an insulating film. Further, time of adding hydrogen ions is reduced and time of manufacture per SOI substrate is reduced. A bond layer is formed over a surface of a first semiconductor wafer and a separation layer is formed below the bond layer by irradiating the first semiconductor wafer with H3+ ions by an ion doping apparatus. H3+ ions accelerated by high voltage are separated to be three H+ ions at a semiconductor wafer surface, and the H+ ions cannot enter deeply. Therefore, H+ ions are added into a shallower region in the semiconductor wafer at a higher concentration than the case of using a conventional ion implantation method.

Abstract: A magnetoresistive memory device 20 includes dies 24 and 38, each of which contains magnetically sensitive material 50. A method 64 of packaging the magnetoresistive memory device 20 entails coupling the die 24 to a substrate 22, forming interconnections 52 between bonding pads 32 on the die 24 to connection sites 54 spaced apart from the die 24. A magnetic shield 36 is bonded to a top surface 30 of the die 24 following formation of the interconnections 52. The die 38 is attached to the magnetic shield 36, interconnections 56 are formed between bonding pads 44 on the die 38 to connection sites 58 spaced apart from the die 38, and a magnetic shield 48 is adhered to the die 38 following formation of the interconnections 56.

Abstract: During a process of forming an active layer of a semiconductor device using a ZnO film, the ZnO film is laser-annealed with an ultraviolet pulsed laser to reduce the resistance of the film, and then oxidation treatment is applied to increase the specific resistance value at a channel portion of the ZnO film, which once has excessively low resistance after the laser annealing, to 103?·cm or more.

Abstract: An image sensor with a plurality of photodiodes that each is adjacent to a first region constructed from a first type of material and comprises a second region constructed from a second type of material. Located between second regions of adjacent photodiodes is a barrier region. The photodiodes are reverse biased to create depletion regions within the substrate. The barrier region limits the lateral growth of the depletion regions and inhibits depletion merger between adjacent photodiodes.

Abstract: In a substrate nitriding method for nitriding a target substrate by allowing a nitrogen-containing plasma to act on silicon on a surface of the substrate in a processing chamber of a plasma processing apparatus, the nitridation by the nitrogen-containing plasma is performed by controlling a sheath voltage Vdc around the substrate to be less than or equal to about 3.5 eV. The sheath voltage Vdc is a potential difference Vp?Vf between a plasma potential Vp in a plasma generating region and a floating potential Vf of the substrate.

Abstract: Apparatuses and methods for manufacturing a solar cell are disclosed. In a particular embodiment, the solar cell may be manufactured by disposing a solar cell in a chamber having a particle source; disposing a patterned assembly comprising an aperture and an assembly segment between the particle source and the solar cell; and selectively implanting first type dopants traveling through the aperture into a first region of the solar cell while minimizing introduction of the first type dopants into a region outside of the first region.

Abstract: A method of forming a semiconductor package includes forming a coating over a first device, attaching the first device to a substrate using an adhesive, encapsulating the first device using an encapsulant material, releasing the first device from the substrate using the adhesive, removing a portion of the encapsulant material that is over the first device to expose the coating, and removing the coating over the first device to expose a portion of the first device.

Abstract: A method for manufacturing a semiconductor device includes: forming a first region and a second region at a main surface of a semiconductor substrate; forming a gate insulating film containing Hf or Zr and oxygen on the first region and the second region; forming a first metallic film on the gate insulating film; forming a second metallic film on the first metallic film; removing a portion of the second metallic film; forming a third metallic film on the second metallic film and a portion of the first metallic film exposed by removing the portion of the second metallic film; and thermally treating so that constituent elements of the second metallic film is diffused into the gate insulating film via the first metallic film.