Patents Examined by W. Tupman
  • Patent number: 4197633
    Abstract: A hybrid mosaic IR/CCD focal plane structure has high detector element packing densities which may be achieved using cost effective planar processing technology. The focal plane structure preferably includes an insulator layer over a silicon substrate which contains integrated circuit CCD signal processing circuitry. A mosaic photovoltaic (Hg,Cd)Te detector array is fabricated on the insulator layer. The photosignals from the detector array are coupled to the CCD circuitry by thin film electrical interconnects together with contact pads which extend through the insulator layer and are exposed at the surface of the insulator layer.
    Type: Grant
    Filed: September 1, 1977
    Date of Patent: April 15, 1980
    Assignee: Honeywell, Inc.
    Inventors: Robert V. Lorenze, Jr., William J. White
  • Patent number: 4196508
    Abstract: A hybrid mosaic IR/CCD focal plane structure is fabricated on a silicon substrate which contains integrated circuit CCD signal processing circuitry. Contact pads are formed which are connected to the signal processing circuitry and which extend above the surface of the silicon substrate. An insulator layer is formed which covers the substrate and the contact pads. The insulator layer is then lapped to form an essentially planar surface with the contact pads exposed. A mosaic detector array is fabricated on the insulator layer, and thin film electrical interconnects are formed from the detectors to the exposed contact pads to couple the photosignals from the detector array to the CCD circuitry.
    Type: Grant
    Filed: September 1, 1977
    Date of Patent: April 8, 1980
    Assignee: Honeywell Inc.
    Inventor: Robert V. Lorenze, Jr.
  • Patent number: 4174561
    Abstract: A photovoltaic energy converter for converting incident radiant energy, such as solar energy, to electrical energy. The converter comprises a cell formed from a plurality of integrally interconnected p-n junction-containing semiconductor wafers. The wafers are stacked end-to-end in the cell so that the respective junctions in each wafer are parallel to each other. The efficiency and performance of the cell is improved, particularly upon exposure to concentrated sunlight, by imposing various conditions on the cell fabrication and design.
    Type: Grant
    Filed: October 27, 1977
    Date of Patent: November 20, 1979
    Assignee: Semicon, Inc.
    Inventors: Robert E. House, Robert A. Irvin, Daniel F. Kane
  • Patent number: 4174562
    Abstract: A metallic ground grid is fabricated by forming a conductor on the isolation barrier of an integrated circuit through openings in a first insulated layer to a depth less than the first insulated layer, forming a second insulated layer on said first conductor to the height of the first insulated layer, and interconnecting selected areas of the integrated circuit and the first conductor through openings in the insulated layers by a second conductor.
    Type: Grant
    Filed: May 16, 1978
    Date of Patent: November 20, 1979
    Assignee: Harris Corporation
    Inventors: Thomas J. Sanders, William R. Morcom, Jacob A. Davis
  • Patent number: 4173821
    Abstract: In the process of fabrication of semiconductor devices, a lead frame hoop supplied from a supply reel is set forward to successively enter into a series of fabricating steps. After having been subjected to pellet bonding, wire bonding and resin-molding, it is wound up about a take-up reel. Baking step is performed with the lead frame hoop wound on the take-up reel. The lead frame hoop unwound from the take-up reel is cut into separate individual semiconductor device units from one another and the measurement of characteristics and the classification of the thus prepared units are carried out with the positions of the units maintained as they were at the cutting step. Accordingly, the process has a smaller number of steps and therefore the production cost is reduced, and the speed of working is improved.
    Type: Grant
    Filed: August 23, 1977
    Date of Patent: November 13, 1979
    Assignee: Hitachi, Ltd.
    Inventors: Masatoshi Yamamoto, Keisuke Makino, Kiyomi Suzukawa, Souichirou Nakamura, Kiyomi Sakai
  • Patent number: 4173064
    Abstract: Excess signal charge generated in response to optical overload of a charge-coupled sensing region is removed from that region by an antiblooming drain implanted in the substrate of the sensing array. The antiblooming drain is separated from the row of sensing regions by a potential barrier produced by a gate electrode associated with the drain. In fabricating the charge-coupled optical imager, the antiblooming drain is self-aligned with the antiblooming gate electrodes by first providing a pair of spaced-apart antiblooming gate electrodes and implanting the drain region into the substrate using the gate electrodes as a mask.
    Type: Grant
    Filed: August 22, 1977
    Date of Patent: November 6, 1979
    Assignee: Texas Instruments Incorporated
    Inventor: Stephen A. Farnow
  • Patent number: 4167804
    Abstract: A monolithic integrated circuit structure having an integral high value surge protection resistor of polycrystalline silicon on a thermally grown thick silicon dioxide plateau having no surface diffusion regions thereunder. The structure can be made by merely adding intermediate steps to existing integrated circuit processing. It is capable of absorbing transients of hundreds of volts.
    Type: Grant
    Filed: August 23, 1978
    Date of Patent: September 18, 1979
    Assignee: General Motors Corporation
    Inventor: Eugene Greenstein
  • Patent number: 4167806
    Abstract: An active zone between a lower electrode deposited on a substrate and an upper electrode constitutes a portion of an amorphous semiconducting layer and is defined either by the dimensions of the upper electrode or by a window formed in an insulating layer. The method of fabrication consists in forming the two electrodes and the two active and insulating layers, the active layer and insulating layer being fabricated from amorphous compounds which are constituted either wholly or in part by the same elements.
    Type: Grant
    Filed: September 22, 1977
    Date of Patent: September 18, 1979
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Pierre Kumurdjian
  • Patent number: 4161814
    Abstract: Disclosed are multi-layer thin-film devices having adjacent insulator-semiconductor layers employing n-or-p-type semiconductors wherein a charge maintained at the insulator-semiconductor interface creates a depletion region that substantially suppresses tunneling of majority carriers while enhancing tunneling of minority carriers. When employed in a metal-insulator semiconductor (MIS) device wherein the semiconductor is a compound such as gallium arsenide (GaAs) or Cadmium Sulfide (CdS) such minority carrier injection substantially increases the luminescence efficiency.
    Type: Grant
    Filed: October 28, 1977
    Date of Patent: July 24, 1979
    Assignee: Cornell Research Foundation, Inc.
    Inventor: Joseph M. Ballantyne
  • Patent number: 4160308
    Abstract: An improved optically coupled isolator uses a glass layer in combination with layers of junction coat material between the emitter and detector to provide greater electrical isolation while preventing potential ionic contamination in the glass from reaching the detector and causing a deterioration in its operating characteristics. The isolator is assembled using standard semiconductor processing techniques so that the cost of manufacture is not substantially increased.
    Type: Grant
    Filed: April 27, 1978
    Date of Patent: July 10, 1979
    Assignee: Fairchild Camera and Instrument Corporation
    Inventors: Thomas Courtney, Vijay K. Lumba
  • Patent number: 4160987
    Abstract: A field effect transistor (FET) with a unique gate structure is disclosed wherein the polycrystalline silicon (polysilicon) gate is self-aligned on its ends with respect to the conductive source and drain regions, and is self-aligned on its sides with respect to the nonconductive field isolation regions. The boundaries of these conductive and nonconductive regions determine the boundaries of the channel region of the FET. This double self-alignment feature results in a polysilicon gate, the lateral dimensions and location of which correlate directly with the lateral dimensions and location of the channel region of the FET. The unique gate fabrication technique employed according to the present invention comprises delineating lithographic patterns twice in the same polysilicon layer using the same oxidation barrier masking layer; whereby the first lithographic pattern delineates the FET device regions, and the next lithographic pattern forms the gate regions wherever the two patterns cross each other (i.e.
    Type: Grant
    Filed: June 6, 1977
    Date of Patent: July 10, 1979
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Dennard, Vincent L. Rideout
  • Patent number: 4159561
    Abstract: Electrical contact to the substrate of a COS/MOS integrated circuit made with a four photomask process and having a well region of conductivity type opposite to that of the substrate is made by ion implanting through the bond pad openings to reconvert portions of the well to the opposite conductivity type thereby allowing contact to be made to the underlying substrate from the top surface.
    Type: Grant
    Filed: December 19, 1977
    Date of Patent: July 3, 1979
    Assignee: RCA Corp.
    Inventor: Andrew G. F. Dingwall
  • Patent number: 4157610
    Abstract: The exposed surface of a semi-insulating compound semiconductor substrate is anodized while light is irradiated to the exposed surface to form a gate insulating film on the substrate between source and drain regions.
    Type: Grant
    Filed: August 18, 1977
    Date of Patent: June 12, 1979
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Kiyoo Kamei, Toshiaki Ikoma, Hirokuni Tokuda
  • Patent number: 4156963
    Abstract: A method for manufacturing a semiconductor device having a cathode layer divided into a plurality of mesa type cathode layer portions and used under pressure applied from the cathode layer side through a pressing plate, the method comprising steps of disposing a flat plate having a lateral width covering at least from the outer edge of a cathode electrode disposed on one outermost cathode layer portion to the outer edge of a cathode electrode disposed on the other outermost cathode layer portion, applying an external pressure through the flat plate, and then disposing the pressing plate.
    Type: Grant
    Filed: December 22, 1977
    Date of Patent: June 5, 1979
    Assignee: Tokyo Shibaura Electric Co., Ltd.
    Inventors: Isamu Tsuji, Nobuo Itazu, Katsuhiko Takigami
  • Patent number: 4156310
    Abstract: The specification describes a semiconductor solar cell and fabrication process therefor wherein a thin N-type gallium arsenide layer is deposited on a larger P-type substrate layer which is selected from the group of III-V ternary compounds consisting of aluminum phosphide antimonide, AlPSb, and aluminum indium phosphide, AlInP. P-type impurities are diffused from the substrate layer into a portion of the thin N-type gallium arsenide layer to form P-type region therein which defines a PN junction in the thin gallium arsenide layer. Thus, the quantity of gallium arsenide required to provide this PN photovoltaic junction layer in the cell is minimized, and the P-type substrate serves as a high bandgap window layer for the cell. Such high bandgap of this window material is especially well suited for efficiently transmitting the blue spectrum of sunlight to the PN junction, thus enhancing the power conversion efficiency of the solar cell.
    Type: Grant
    Filed: March 17, 1978
    Date of Patent: May 29, 1979
    Assignee: Hughes Aircraft Company
    Inventor: G. Sanjiv Kamath
  • Patent number: 4155154
    Abstract: Wound foil electrolytic capacitor sections are anodized after winding. After removal of the formation electrolyte, the sections are rinsed, dried, and impregnated with working electrolyte. The sections are assembled by usual means into capacitors.
    Type: Grant
    Filed: October 6, 1977
    Date of Patent: May 22, 1979
    Assignee: Sprague Electric Company
    Inventors: Mark Markarian, Francis J. Gamari, Franz S. Dunkl
  • Patent number: 4153984
    Abstract: A method for fabricating a variable threshold IGFET free of parasitic effects and the "floating gate" effect.The method comprises forming a semi-conductive substrate of a first conductivity type material, forming a pair of laterally spaced diffusion regions of opposite conductivity type to the substrate material adjacent one surface of the substrate and forming a variable thickness oxide layer having a portion of minimum thickness with a predetermined width at least partially overlying the interstitial portion of the substrate, a portion of intermediate thickness substantially greater than the minimum thickness and partially overlying the interstitial substrate portion and at least one of the pair of spaced diffusion regions, and a remaining portion of maximum thickness substantially greater than the intermediate thickness.
    Type: Grant
    Filed: July 22, 1977
    Date of Patent: May 15, 1979
    Assignee: Nitron Corp.
    Inventor: Yukun Hsia
  • Patent number: 4152823
    Abstract: A multi-layer integrated semiconductor circuit interconnection structure with a first layer formed of a refractory metal sandwich including outer layers of silicon and a core of refractory metal providing a high temperature low ohmic contact assembly, an insulating layer formed on the first layer, and a patterned metal layer formed on the insulating layer to interconnect with the refractory layer and semiconductor device to provide an integrated circuit assembly.
    Type: Grant
    Filed: April 28, 1977
    Date of Patent: May 8, 1979
    Assignee: Micro Power Systems
    Inventor: John H. Hall
  • Patent number: 4151631
    Abstract: An IC manufacturing method that eliminates the need for separate pad area and allows polysilicon MOS transistor gates to be contacted directly. Present silicon gate process techniques are utilized up to and including the formation of the gate oxide layer, with areas etched through to the substrate. Then polysilicon and silicon nitride are deposited preferably in the same deposition equipment. The polysilicon interconnect and gate pattern is selectively etched for both silicon nitride and polysilicon. Next, the gate oxide exposed by the previous step is removed and phosphorous is diffused into the exposed silicon substrate surfaces. The initial nitride thickness is chosen such that after phosphorous predeposition and subsequent removal of phosphorous glass, a thin layer of silicon nitride is left. A silicon oxide protective layer is then grown over the exposed silicon substrate surfaces. The remaining silicon nitride is removed and a phosphosilicate glass is deposited over the entire surface.
    Type: Grant
    Filed: May 18, 1977
    Date of Patent: May 1, 1979
    Assignee: National Semiconductor Corporation
    Inventor: Thomas Klein
  • Patent number: RE30251
    Abstract: Method of making an insulated gate field effect transistor is described in which the surface of a silicon semiconductor is covered in whole or in part with a layer of a masking material which masks against oxidation, such as silicon nitride. Areas of the silicon surface are exposed for the source and drain regions, leaving the oxidation mask over the future channel. When the source and drain regions have been made, as for example by diffusion, the device is subjected to oxidation, causing the growth of a thick oxide which sinks into the silicon surface where it is not masked by the oxidation mask. Among the advantages obtained are fewer precise masking steps, a flatter device surface, and reduced gate overlap of the source and drain.
    Type: Grant
    Filed: May 23, 1978
    Date of Patent: April 8, 1980
    Assignee: U.S. Philips Corporation
    Inventor: Else Kooi