Abstract: A unitary device comprising a millimeter wave source embedded in a block which integrated simultaneously the bias means, the heat-dissipation means and the impedance-matching arrangements. The source, which is an avalanche diode of very small dimensions, is welded to a dissipating mounting comprising a central platform with a slight central projection. Subsequently, the diode is surrounded by a glass ring whose central opening is filled with polymerizable resin. Mechanical grinding is carried out in order to bare the top layer of the diode and metallizing performed in order to provide a supply terminal for DC. In an application of the invention to a millimeter waveguide, the supply contact is formed by a simple transverse metal wire leaving the walls of the waveguide through insulating lead-throughs.

Abstract: A silicon-on-sapphire, or silicon-on-spinel (SOS), epitaxial detector and readout structure and method of preparation. The present structure comprises silicon devices formed on sapphire, or spinel, substrates in which delineated silicon detectors, and electrically and optically isolated charge-coupled devices (CCDs), are used for signal readout from the detectors. The structure may be placed at the focal plane of an imaging infrared (IR) system for signal readout therefrom.

Abstract: The specification describes a self-aligning masking technique for the fabrication of charge coupled device-metal oxide semiconductor (CCD/MOS) transistor combinations. Both the CCD devices and the output MOS transistors are formed on the same semiconductor substrate during the same processing steps. Two layers of polycrystalline silicon, isolated from each other by a layer of dielectric material and isolated from the semiconductor substrate by another dielectric layer are used to form two sets of partially overlapping semiconductor strips. These strips and predetermined portions of the substrate are then doped, with a conductivity determining impurity opposite the conductivity type of the substrate. This process produces two self-aligned sets of gate electrodes for a two-phase or a four-phase CCD device and also produces two output self-aligned gate field effect transistors at the end of the CCD array.

Abstract: A process intended for combining the "flip-chip bonding" technique with a method yielding diodes of very thin substrate forming mesa units or clumps etched out in a dielectric block embedding the semiconductor body. The process comprises, starting from a semiconductive wafer, a double mesa etching and a double lapping, each of them carried out on each side of the wafer, due to a thick dielectric layer and a thick metallic support respectively brought in at the right moment.

Abstract: A method of forming a silicon solar energy cell, which comprises forming an electron generating junction on a single crystal silicon wafer and thereafter using a saw having a diamond blade to cut through the wafer and the junction formed therein.

Abstract: A method is provided for producing solar cells employing slightly curved or nearly flat monocrystalline silicon ribbons. The ribbons are formed by cutting or slicing monocrystalline hollow tubes along their lengths, the tubes having been formed according to crystal growing processes disclosed in U.S. Pat. No. 3,591,348.

Abstract: A process of forming a composite semiconductor integrated circuit by forming one or more epitaxial layers of semiconductor material on a semiconductor substrate, forming pedestals by etching partially through said epitaxial layers to form regions projecting from said substrate and etching through said epitaxial layers to form stress relieving channels in the substrate surrounding the pedestals. A thick layer of easily removable material such as an evaporated layer of chromium plus gold and a plated layer of gold is deposited of sufficient thickness to provide good mechanical support, and the substrate is removed by lapping, grinding or etching until at least the stress relieving channels are exposed thereby forming separate semiconductor elements containing said epitaxial regions.

Abstract: A fabrication method for providing electrical isolation between transistors such as field effect transistors (FETs) which are fabricated on the same semiconductive substrate is described that uses a single doping step to form both the channel stopper field doping and the FET channel doping. An example of an n-channel FET embodiment is described wherein an extra p-type doping is provided in the field region which serves to prevent parasitic conductive channels from occurring under the thick field oxide. Such parasitic channels can undesirably cause electrical shorting between adjacent FETs of an integrated circuit. Extra p-type doping is also provided in the FET channel region and serves to raise the gate threshold voltage of the enhancement-mode FET to a level suitable for integrated circuit operation. In the described method a single implantation or diffusion doping step provides both the field and channel doping regions, thereby reducing the number of processing steps.

Abstract: Methods for monolithic integrated circuit construction are presented wherein component device-isolating region self-alignment is provided and also, where an element of the device is provided through independent dopant provision steps to allow design flexibility in providing that device element and associated integrated circuit devices. The method is especially applicable to bipolar device construction.

Abstract: A field effect transistor and method of making the same wherein a semi-conductor layer is placed on an insulating substrate, and wherein the gate region is separated from source and drain regions of a like conductivity type to that of the source and drain regions but of reduced conductivity, the gate electrode and gate region of the layer being of generally reduced length, and the gate region being of greatest length on its surface closest to the gate electrode. This is accomplished by initially creating a relatively large gate region of one polarity, and then reversing the polarity of a central portion of this gate region by ion bombardment, thus achieving a narrower final gate region of the stated configuration.

Abstract: An integrated circuit having a direct metal contact to a buried layer is fabricated by first diffusing said buried layer into a substrate and growing thereon an epitaxial layer. After emitter diffusion into the epitaxial layer and emitter oxidation, a sink hole is etched through the oxide mask, the epitaxial layer, and into the buried layer. An oxide layer is then grown over the surface of the sink hole; which oxide layer is then coated with a negative photoresist. The negative photoresist is exposed to collimated light at an incident angle which results in an unexposed area of photoresist at the bottom of the sink hole. The unexposed area is washed off during developing and the exposed oxide etched away, thereby exposing the buried layer. A metal may be deposited, for example, by evaporation, thus creating a direct metal contact to the buried layer.

Abstract: Ohmic contacts to p-type mercury cadmium telluride are prepared by depositing a Column IB metal on a surface of the p-type mercury cadmium telluride, depositing a buffer material on the Column IB metal, and contacting the buffer material with a bonding material which is capable of alloying with the Column IB metal. The buffer material prevents alloying between the Column IB metal and the bonding material.

Abstract: Electrical contact to the substrate of a COS/MOS integrated circuit made with a four photomask process and having a well region of conductivity type opposite to that of the substrate is made by ion implanting through the bond pad openings to reconvert portions of the well to the opposite conductivity type thereby allowing contact to be made to the underlying substrate from the top surface.

Abstract: A method of manufacturing a metal silicide pattern with respect to which two electrode zones are to be provided in a self-registering manner. According to the invention the pattern is provided in the form of a layer of polycrystalline silicon and, by selective oxidation and masking, only the upper surface of the pattern is exposed to the silicide formation so that passivation problems and short circuit are avoided. The use of silicides which cannot withstand high temperatures is also possible.

Abstract: A metal film is deposited on both sides of a semiconductor wafer. A conductive support layer, e.g. gold, is deposited on one of the metal film layers. Using standard procedures, the semiconductor material is then etched to form a plurality of semiconductor devices on the support. A photoresist is next applied over the device side of the support. Windows are opened into the photoresist above each of the devices. A gold wire is attached near the edge of each device so that the devices are each electrically connected in parallel to all of said devices and to said support. A copper heat capacitor is now plated on each device. The gold wires and the photoresist are removed, leaving a copper heat capacitor on the semiconductor device. A copper heat can be formed on the device, with or without formation of the copper heat capacitor, but always after formation of the device per se.

Abstract: A method for fabricating an indium antimonide semiconductor device which includes anodizing through a portion of the thickness of an indium antimonide substrate containing an active impurity of a first type; selectively ion implanting an active impurity of a second type into the indium antimonide substrate; annealing; providing for ohmic electrical contact between preselected regions of the indium antimonide substrate and subsequently applied electrical contacts; and depositing a plurality of electrical contacts, a predetermined number of which are in ohmic electrical contact with the preselected regions of the substrate to thereby provide the semiconductor device; and semiconductor device obtained thereby.

Abstract: Semiconductor devices are mounted on corresponding lead frames by being inserted into apertures of a masking member in a desired registration with the lead frame strip.

Abstract: A method for fabrication of an n-channel MIS device is composed of forming a source region and a drain region in the surface of a p-type semiconductor substrate by the diffusion of a first n-type impurity through a mask pattern including an insulator gate film, forming a first silicate glass film on the surface of the resultant substrate, providing windows for source, drain and gate contacts in the first silicate glass film, diffusing a second n-type impurity through the windows for source and drain contacts to form n-type high impurity concentration regions, selectively removing a second silicate glass film formed simultaneously with the diffusion of the second n-type impurity while leaving the portions of the second silicate glass film except at least the windows for source, drain and gate contacts, and providing metal contacts in the windows.

Abstract: Method of manufacturing a transistor which includes an emitter pattern and a base pattern and provides a predetermined current amplification factor, and said method includes a step of measuring a current amplification factor of a monitor transistor during the manufacturing process, the characteristic feature of said method includes the steps of forming a monitor transistor pattern providing the same amplification factor as the semi-conductor device to be manufactured, providing additional portions to an emitter pattern and a base pattern of said monitor transistor pattern, contacting a probe of the measuring apparatus to said additional portions and effecting the measurement of the amplification factor of the monitor transistor.

Abstract: A transducer assembly for measuring absolute pressure utilizing a glass substrate and a thin silicon diaphragm upon which is diffused a piezoresistive bridge circuit. Bridge circuit components are properly oriented and connected to bonding pads formed on the silicon. The glass substrate has a circular well formed therein having a diameter at least as large as the diameter of the diaphragm. Conducting leads are deposited on the glass substrate in a pattern matching that of the bonding pads on the silicon. The silicon is bonded to the glass substrate with the silicon diaphragm overlying the well in the glass and the bonding pads overlying the conducting leads deposited on the glass. The bond provides a hermetic seal around the well, trapping a predetermined pressure therein which serves as a reference pressure. Ambient pressure variations cause stress variation in the diaphragm, resulting in unbalance of the bridge which can be sensed with associated circuits to give an indication of the ambient pressure.