Patents Examined by W. Tupman
  • Patent number: 4127931
    Abstract: In a method for fabricating a semiconductor device, a polycrystalline film deposited on a main surface of a substrate is subjected to selective oxidation to form polycrystalline silicon electrode wiring paths separated by silicon oxide. An impurity of a conductivity type opposite to that of the substrate is introduced through at least one of the wiring paths into the substrate. Also disclosed is a novel semiconductor device fabricated according to this process which has a reduced junction area and a shortened junction-to-electrode distance.
    Type: Grant
    Filed: November 2, 1977
    Date of Patent: December 5, 1978
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Hiroshi Shiba
  • Patent number: 4126931
    Abstract: Several junction-type semiconductor chips, specifically NPN transistors, are simultaneously produced by mesa technique from a semiconductor wafer by adhering to one major surface thereo a supporting structure including a bonding layer of wax, similarly adhering a protective layer of a relatively soft material -- likewise a wax -- to the opposite major wafer surface, and dividing the wafer into chips temporarily held together by the supporting structure. The last-mentioned step involves a splitting of the protective layer into isolated sections by making incisions in that layer cutting into the underlying wafer body, followed by an erosion of the semiconductor material of that body by an etching solution to form channels which extend completely across the wafer and terminate at the supporting structure, these channels being widened in the immediate vicinity of the protective layer to form undercuts. A continuous passivating film is applied, e.g.
    Type: Grant
    Filed: April 11, 1977
    Date of Patent: November 28, 1978
    Assignee: SGS-ATES Componenti Elettronici S.p.A.
    Inventors: Luciano Gandolfi, Rudolf Rocak
  • Patent number: 4125933
    Abstract: An IGFET integrated circuit memory cell structure utilizing a capacitor with increased charge storage capability, and a method making the same. The capacitor includes a high impurity concentration region having the same conductivity type as the substrate. An island of opposite conductivity type is inset in the region and a conductive field plate overlies the island. The structure also includes a transfer transistor in which the source region is adjacent the capacitor and overlaps the island region therein. Activation of the transistor serves to transfer the charge stored in the capacitor to the drain region where it can be read by external circuitry. In the method, the high concentration region and island in the capacitor are formed by successive ion implantation steps.
    Type: Grant
    Filed: May 2, 1977
    Date of Patent: November 21, 1978
    Assignee: Burroughs Corporation
    Inventors: Steven M. Baldwin, Donald L. Henderson, Sr., Joel A. Karp
  • Patent number: 4125252
    Abstract: A power semiconductor assembly in which two metallic heat sinks with inner planar surfaces clamp between these surfaces a housing of a power semiconductor therein at a set clamping pressure. The casing has planar surfaces against which the inner planar surfaces of the heat sinks are clamped. Three threaded rod assemblies are assembled in three sets of recesses on the heat sinks controlling the pressure applied to the semiconductor assembly. Each heat sink has three recesses communicating with outer surfaces thereof aligned axially with corresponding similar recesses of the other heat sink. The rod assemblies each have a pair of threaded rods joined coaxially by a molded element made of, for example, porcelain, or a resin epoxy such as "Araldite", or a mica-glass composition. Nuts are threaded on the two rods and a calibrated elastic washer on one rod hold the entire assembly at the desired clamping pressure.
    Type: Grant
    Filed: April 21, 1977
    Date of Patent: November 14, 1978
    Assignee: Jeumont-Schneider
    Inventor: Robert Jouanny
  • Patent number: 4124933
    Abstract: A method of manufacturing a semiconductor device in which a masking layer is formed on part of the surface of a deposited layer of relatively high resistivity polycrystalline semiconductor material present on an insulating layer provided at a surface of a semiconductor body or body part and a relatively low resistivity conductive region having a substantially uniform narrow line width is defined in the polycrystalline layer by effecting a diffusion process to laterally diffuse a doping element into a portion of the polycrystalline layer underlying an edge portion of the masking layer without diffusing the doping element through the insulating layer into the semiconductor body or body part.
    Type: Grant
    Filed: January 21, 1977
    Date of Patent: November 14, 1978
    Assignee: U.S. Philips Corporation
    Inventor: Keith H. Nicholas
  • Patent number: 4124934
    Abstract: A method of manufacturing a semiconductor device in which a layer of polycrystalline material having a high impurity concentration is used prior to the diffusion of a thin region having strong surface concentration and prior to providing a contact to the said region.The polycrystalline layer is comparatively thick prior to the diffusion and is reduced in thickness before the metal contact is provided.
    Type: Grant
    Filed: February 1, 1977
    Date of Patent: November 14, 1978
    Assignee: U.S. Philips Corporation
    Inventor: Michel De Brebisson
  • Patent number: 4123834
    Abstract: A method for making an overlapping electrode structure on an insulation layer comprising selectively etching a conducting layer on the insulation layer to form channels which are oxidized to form conducting ribbons surrounded by an insulating blanket. Contact windows are then opened in selected areas of the insulating blanket such that a conducting material cooperates with the conducting ribbons to form the overlapping electrode structure. In an alternative method, a bilayer structure comprising layers of first and second etching materials is formed on the insulating layer. Channels are then etched in selected portions of the bilayer structure and etch stops are formed along one side wall of the channel through the bilayer structure. The exposed surfaces of the insulation layer and first etching material are then simultaneously etched to form a sloped area in the surface of the insulation layer as a consequence of differential etching rates of the insulation layer and the first etching material.
    Type: Grant
    Filed: June 14, 1977
    Date of Patent: November 7, 1978
    Assignee: Westinghouse Electric Corp.
    Inventor: Nathan Bluzer
  • Patent number: 4121333
    Abstract: A new method of manufacturing a two-phase charge-transfer device operating by the charge-coupled technique, in which the asymmetry means associated with each group of electrodes are constituted by impurity barriers implanted in the semiconductor substrate and are automatically positioned in relation to the electrodes, in particular by carrying out implantation operations through masks constituted by films of silicon nitride and by the electrodes themselves, the films of silicon nitride subsequently being completely removed.This method makes it possible to create linear charge-transfer registers and photo-sensitive matrices.
    Type: Grant
    Filed: May 31, 1977
    Date of Patent: October 24, 1978
    Assignee: Thomson-CSF
    Inventors: Jean Luc Berger, Michel Bourrat, Yves Thenoz, Daniel Woehrn
  • Patent number: 4119993
    Abstract: A GaAs mosfet comprises a p-type gallium arsenide single crystal having two grooves formed therein, each groove containing a layer of indium, a layer of dopant overlying the indium and a layer of Al.sub.2 O.sub.3 overlying the dopant, each groove overlying a respective n.sup.+ region of the gallium arsenide, the surface of the gallium arsenide single crystal on each side of each groove comprising native oxide to a depth contiguous to the n.sup.+ regions, and the layers of dopant being in contact with the junctions between the n.sup.+ regions and the native oxides. A flat contact pad covers the native oxide between the grooves and is in contact with the Al.sub.2 O.sub.3 of both grooves, a second contact pad covers the native oxide on the remaining side of one groove and is in contact with the dopant via an electrically ruptured part of the Al.sub.2 O.sub.
    Type: Grant
    Filed: December 30, 1976
    Date of Patent: October 10, 1978
    Assignee: National Research Development Corporation
    Inventors: Hans Ludwig Hartnagel, Burhan Bayraktaroglu
  • Patent number: 4117587
    Abstract: A pair of field-effect transistors (hereinafter referred to as FETs) of p-channel type and n-channel type, respectively, both to be electrically actuated in a depletion mode, are formed on a single semiconductor substrate, for instance, a single silicon substrate, and both sources or both drains are connected to each other, or the source of one FET and the drain of the other FET are connected to each other, whereby the pair of FETs are series-connected, and the gate electrode of each FET is connected to the drain electrode or the source electrode that is not series connected in the above-mentioned way, respectively, of the other FET. The device is characterized in that each FET has each back-gate electrode region behind the channel. Preferably, such back-gate regions are high-doped diffused regions.When a voltage of specified range is applied across both non-series-connected electrodes, i.e.
    Type: Grant
    Filed: August 6, 1976
    Date of Patent: October 3, 1978
    Assignee: Matsushita Electronics Corporation
    Inventors: Gota Kano, Hitoo Iwasa
  • Patent number: 4114254
    Abstract: A semiconductor device and method of making the same is disclosed having a surface passivation film of a polycrystalline silicon layer containing 2 to 45 atomic percent of oxygen atoms.The polycrystalline silicon layer is locally electrically insulated by oxidizing throughout the thickness of the layer.The local oxidizing treatment causes the polycrystalline or silicon layer to pattern.
    Type: Grant
    Filed: March 22, 1976
    Date of Patent: September 19, 1978
    Assignee: Sony Corporation
    Inventors: Teruaki Aoki, Motoaki Abe
  • Patent number: 4114255
    Abstract: A floating gate storage device in which the channel is maintained at a first doping concentration to provide a low threshold voltage and preselected portions or regions along the sides of the channel are maintained at a second higher doping concentration to enhance programming of the device. These regions are formed as part of the "front-end" processing of the substrate while forming channel stops, thus no additional processing is required.
    Type: Grant
    Filed: May 2, 1977
    Date of Patent: September 19, 1978
    Assignee: Intel Corporation
    Inventors: Phillip J. Salsbury, George Perlegos, William L. Morgan
  • Patent number: 4114256
    Abstract: A self-aligned technique for making metal-to-junction contacts in a shallow-junction large-scale-integrated device involves opening very small contact windows in the intermediate insulating layer of the device. These windows respectively overlie only limited central regions of the junctions. Impurities are then applied via the contact windows to provide deeper junction portions directly below the windows. As a result, metallic contact regions subsequently deposited in the windows are exactly aligned with respect to the deeper junction portions. Penetration or spiking of the junctions by the metallic regions is thereby significantly reduced.
    Type: Grant
    Filed: June 24, 1977
    Date of Patent: September 19, 1978
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Louis Robert Thibault, Leopoldo Dy Yau
  • Patent number: 4114257
    Abstract: A method for fabricating a three-dimensional integrated optical circuit is disclosed. Selective liquid phase epitaxy is utilized to grow active electro-optic devices consisting of an I-bar mesa laser, a directional-coupler switch and a channel-waveguide modulator, and a passive electro-optic device consisting of a directional-coupler wherein all devices in the integrated optical circuit as grown on the substrate are interconnected by means of a three-dimensional waveguide structure. The active and passive device section of the substrate consists of an open area to allow for the selective epitaxial growth of an I-bar mesa laser or the formation of a metallized pattern in the fabrication of directional-coupler switches, channel-waveguide modulators and directional-couplers. Theses devices are interconnected by means of an optical waveguide structure which may have the form of a single or double heterojunction structure of the ridge waveguide type.
    Type: Grant
    Filed: September 23, 1976
    Date of Patent: September 19, 1978
    Assignee: Texas Instruments Incorporated
    Inventor: David Walter Bellavance
  • Patent number: 4109372
    Abstract: The invention disclosed pertains to a method for the manufacture of an integrated insulated gate field effect transistor semiconductor device wherein a silicon gate structure is simultaneously formed with a composite layer of silicon and a conductive silicide forming metal which upon subsequent annealing forms a conductive metallic silicide compound within the via interconnection means. The aforesaid structure is accomplished utilizing a photoresist lift-off technique as a masking material as well as a substance per se or in combination with other materials to define evaporative conductive metal dimensions on a diffused silicon substrate.
    Type: Grant
    Filed: May 2, 1977
    Date of Patent: August 29, 1978
    Assignee: International Business Machines Corporation
    Inventor: Robert M. Geffken
  • Patent number: 4107834
    Abstract: Correlated electrolytic capacitors having a standard diameter and a method for producing the same in which each capacitor has a constant foil length providing operation at a standard frequency with an equivalent series resistance not appreciably in excess of the lowest ESR for the standard frequency.
    Type: Grant
    Filed: December 20, 1976
    Date of Patent: August 22, 1978
    Assignee: Sprague Electric Company
    Inventor: James J. Kolkowski
  • Patent number: 4106184
    Abstract: A plurality of regularly spaced solid electrolyte capacitor bodies are held by their anode leads. A group of cathode lead wires are held at the same spacing and an exothermically alloyable fuse strand is laid at right angles over the held cathode leads and attached thereto. The fuse strand is cut in the spaces between adjacent lead wires and the held lead wires are registered with the held capacitor bodies. An insulative layer is provided between each body and an adjacent lead wire. The free ends of the cut fuse segments are connected to the counterelectrodes of the adjacent capacitor bodies and the bodies with attached fuse segments are encapsulated as by molding.
    Type: Grant
    Filed: May 16, 1977
    Date of Patent: August 15, 1978
    Assignee: Sprague Electric Company
    Inventors: Lawrence E. Fournier, Theodore M. Jasiewicz, William M. Milton
  • Patent number: 4104784
    Abstract: A novel MOSFET circuit and method of manufacture utilizing a double ion implant process for manufacturing a low voltage high performance n-channel device that includes an enhancement transistor inverter combined with a depletion transistor load. The process starts with high resistivity material and uses a first ion implant process to dope the field region and to give the required threshold voltage for an enhancement device. A second ion implant is used to dope the channel region for the depletion device.
    Type: Grant
    Filed: April 1, 1977
    Date of Patent: August 8, 1978
    Assignee: National Semiconductor Corporation
    Inventor: Thomas Klein
  • Patent number: 4104785
    Abstract: In fabricating a large-scale semiconductor integrated circuit, a wiring layer within each unit cell is formed of a conductive material which is hard and highly resistant to corrosion, and test pads for each unit cell are formed of a conductive material which is soft and low resistant to corrosion. After testing each unit cell by using the test pads, the test pads are etched away. If necessary, pad relocation wiring which is used to substitute a good unit cell for a bad unit cell may be formed of the hard and highly corrosion-resistant conductive material, and an intercell wiring layer may be formed of the soft and low corrosion-resistant conductive material.
    Type: Grant
    Filed: February 23, 1976
    Date of Patent: August 8, 1978
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Hiroshi Shiba, Kenji Kani
  • Patent number: 4103415
    Abstract: An oxide dielectric layer is interposed between the polysilicon gate and the contact hole to the source or drain of an insulated-gate field-effect transistor to prevent electrical shorts between the gate and metal contact to the source or drain. The oxide dielectric layer enables the contact hole to be extremely close to the polysilicon gate without electrical shorts occurring therebetween, thereby eliminating the need for a minimum separation between the gate and contact hole.
    Type: Grant
    Filed: December 9, 1976
    Date of Patent: August 1, 1978
    Assignee: Fairchild Camera and Instrument Corporation
    Inventor: James A. Hayes