Abstract: Embodiments of the invention provide a substrate with a device layer having different crystal orientations in different portions or areas. One layer of material having one crystal orientation may be bonded to a substrate having another crystal orientation. Then, a portion of the layer may be amorphized and annealed to be re-crystallized to the crystal orientation of the substrate. N- and P-type devices, such as tri-gate devices, may both be formed on the substrate, with each type of device having the proper crystal orientation along the top and side surfaces of the claimed region for optimum performance. For instance, a substrate may have a portion with a <100> crystal orientation along a top and sidewalls of an NMOS tri-gate transistor and another portion having a <110> crystal orientation along parallel top and sidewall surfaces of a PMOS tri-gate transistor.

Abstract: An organic thin film transistor (OTFT) array panel includes a substrate, a data line formed on the substrate, a source electrode connected with the data line, a drain electrode, including a portion facing the source electrode, an insulating layer formed on the source electrode and the drain electrode and having an opening and a contact hole, an organic semiconductor positioned in the opening and at least partially contacting the source electrode and the drain electrode, a gate insulator formed on the organic semiconductor, a stopper formed on the gate insulator, a gate line crossing over the data line and including a gate electrode formed on the stopper, and a pixel electrode connected to the drain electrode through the contact hole.

Abstract: The normally on transistor comprises a source, a drain and a channel. The source, drain and channel materials are chosen such that, for a NMOS type transistor, the electronic affinity of the drain material is lower than the electronic affinity of the channel material and the electronic affinity of the source material is higher than the electronic affinity of the channel material. Moreover, the materials are selected such that, for a PMOS type transistor, the upper level of the valence band of the drain material is higher than the upper level of the valence band of the channel material and the upper level of the valence band of the source material is lower than the upper level of the valence band of the channel material.

Abstract: A semiconductor device includes a conductive pattern disposed on a substrate, a first interlayer dielectric layer disposed on the substrate and the conductive pattern, a first dummy pattern disposed on the first interlayer dielectric layer and partially overlapping the conductive pattern, a second interlayer dielectric layer disposed on the first interlayer dielectric layer and the first dummy pattern, a second dummy pattern disposed on the second interlayer dielectric layer and partially overlapping the conductive pattern, a third interlayer dielectric layer disposed on the second interlayer dielectric layer and the second dummy pattern, and a contact plug that penetrates the third interlayer dielectric layer, the second interlayer dielectric layer, and the first interlayer dielectric layer to contact the conductive pattern, the contact plug arranged between the first dummy pattern and the second dummy pattern, the contact plug abutting the first dummy pattern and the second dummy pattern.

Abstract: A semiconductor integrated circuit fabrication method according to this invention includes: a step of forming a pair of first device forming regions and a pair of second device forming regions in a surface layer portion of a semiconductor substrate by surrounding each of the regions by device isolation; a step of forming a first oxide film covering the surface of the semiconductor substrate after the preceding step; a step of removing an intended portion of the first oxide film to expose the pair of second device forming regions; a step of forming a pair of heterojunction structures, by selective epitaxial growth, on the pair of second device forming regions thus exposed; a step of forming a second oxide film covering the surface of the substrate after the preceding step; and a step of forming a pair of gate electrodes above each of the pair of first device forming regions and the pair of second device forming regions, whereby a normal complementary MOS transistor and a heterojunction complementary MOS transi

Abstract: In a transistor of the invention, at a boundary between gate oxide 112 formed on a silicon substrate 101 of a device formation region 10 and a device isolation film 110 adjoining the gate oxide 112, a thickness D? of the gate electrode 114 is set larger than a uniform thickness D of the gate electrode 114 on the gate oxide 112. A height difference A between a surface of the gate oxide 112 and a surface of the device isolation film 110, a width B of a step portion 110b of the device isolation film, and the thickness D of the gate electrode 114 in its uniform-thickness portion satisfy relationships that D>B and A/D+(1?(B/D)2)0.5>1. By ion implantation via the gate electrode 114 and the gate oxide 112, an impurity is added into a surface portion of the silicon substrate 101 at an end portion 11 of the device formation region, the impurity having concentrations higher than in the surface portion of the silicon substrate 101 in the electrode uniform portion 12 of the device formation region.

Abstract: A resist region covering the gate terminal and lead and between a passivation layer and a gate insulating layer is used to protect the gate terminal and lead. The resist region is located at a scribing line on margin of the color filter substrate of a panel, thereby the resist region can protect the passivation layer and the gate insulating layer from cracking, and the gate terminal and the lead from corrosion after a portion of the color filter substrate is removed along the scribing line.

Abstract: The image pickup device of the invention has a path deeper in a semiconductor substrate, than a region wherein a channel is formed, upon turning on a first MOS transistor, under a gate thereof. The path is arranged by forming a P-type layer for forming a potential barrier, within a P-type well excluding a region below the gate of the first MOS transistor. Thus, even when the first transfer MOS transistor is securely turned off at accumulation, carriers overflowing from a photodiode can flow into the path, thereby enabling to accumulate the carriers, overflowing from the photodiode, in a carrier accumulation region. Such structure allows to suppress a dark current generation from an interface of a gate oxide film of the first transfer MOS transistor, and also to expand the dynamic range of the image pickup device by the carriers overflowing from the photodiode and flowing through the path into the carrier accumulation region.

Abstract: Embodiments relate to a CMOS image sensor. In embodiments, the CMOS image sensor may include a semiconductor substrate, a photodiode, a first conduction type impurity region, a first insulating layer, a conduction layer, and a second insulating layer. The semiconductor substrate may have a trench in which a device isolation layer is to be formed. The photodiode may be formed in an active region of the semiconductor substrate, and the first conduction type impurity region may be formed in sidewalls of the trench. The first insulating layer may be formed inside the trench, and a conduction layer may be formed inside the trench and doped with second conduction type impurities. A second insulating layer may be formed inside the trench.

Abstract: In a memory cell array are arranged a plurality of cell units having memory cells and selection gate transistors to select the memory cell. A first selection gate line includes a control gate of the selection gate transistors. A second selection gate line is formed above the first selection gate line. The first selection gate line has a first gate electrode, a first inter-gate insulating film and a second gate electrode superimposed in this order. The first inter-gate insulating film has a first opening portion through which the first gate electrode and the second gate electrode come into contact with each other. A contact material is formed on the first selection gate line, and electrically connects the first selection gate line and the second selection gate line with each other. The contact material is arranged on the first selection gate line on which the first opening portion is not arranged.

Abstract: A semiconductor device 1 is a vertical MOSFET, and includes a plurality of unit cells 10 and a gate electrode 20. Each unit cell 10 includes a back-gate region 12 formed in the semiconductor substrate and a source region 14 formed in the semiconductor substrate so as to adjacently surround the back-gate region 12 in a plan-view. A portion of the back-gate region 12 is adjacent to the gate electrode 20. More specifically, the back-gate region 12 is in a rectangular plan-view shape, and adjacent to the gate electrode 20 at a pair of opposing sides out of the four sides thereof.

Abstract: A semiconductor mechanical quantity measuring apparatus in which the reverse surface of a strain-detecting semiconductor element is bonded to an object of measurement, and a member having a small elastic modulus is interposed between the wiring board for supporting the strain-detecting semiconductor element and the strain-detecting semiconductor element. It then becomes possible to reduce an undesirable effect that the rigidity and thermal deformation of the wiring board have on the strain-detecting semiconductor element, while supporting the strain-detecting semiconductor element.

Abstract: A unit HBT and a unit FET are arranged to be adjacent to each other through an isolation region and a base electrode of the unit HBT is connected to a source electrode of the unit FET to form a unit element, and a plurality of unit elements are connected to form an active element. This makes it possible to implement the active element in which a current is not likely to concentrate on the unit element and no destruction is generated by the second breakdown. Moreover, although a buried gate electrode structure is used to ensure a withstand pressure in the unit FET, a buried portion is structured not to be diffused to an InGaP layer, and thereby it is possible to prevent Pt from being abnormally diffused. Furthermore, a selection etching can be used for a formation of an emitter mesa, that of a base mesa, that of a ledge in the unit HBT, and a gate recess etching in the unit FET, and a good reproducibility can be obtained.