Abstract: The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protective layer on an insulator which is on a conductive layer.

Abstract: A nitride semiconductor light emitting device including: a first nitride semiconductor layer, an active layer formed on the first nitride semiconductor layer and including at least one barrier layer grown under hydrogen atmosphere of a high temperature; and a second nitride semi conductor layer formed on the active layer, and a method of fabricating the same are provided. According to the light emitting device and method of fabricating the same, the light power of the light emitting device is increased and the operation reliability is enhanced.

Abstract: Provided is a micro-mechanical structure and method for manufacturing the same, including a hydrophilic surface on at least a part of a surface of the micro-mechanical structure, so as to prevent generation of an adhesion phenomenon in the process of removing a sacrificial layer to release the micro-mechanical, wherein the sacrificial layer comes into contact with the surface of the micro-mechanical structure.

Abstract: An organic TFT that has an improved contact between source and drain electrodes and an organic semiconductor layer, a method of manufacturing the same, and an organic light emitting display device having the organic TFT are disclosed. The organic TFT includes a substrate, a gate electrode disposed on the substrate, a gate insulating film covering the gate electrode, a source electrode and a drain electrode disposed on the gate insulating film, a peel-off preventive layer disposed on the gate insulating film to contact at least a portion of end surfaces of the source and drain electrodes, and an organic semiconductor layer that contacts the source and drain electrodes.

Abstract: Methods are disclosed for electrically connecting I/O bond-pads on a chip to corresponding I/O bond-pads on a substrate. In an exemplary method a respective stud-bump is formed on each I/O bond-pad on the substrate. The stud-bumps can be made of a fusible material, or a layer of fusible material can be formed on each I/O bond-pad on the chip. The chip is flipped and placed on the stud-bumps such that the I/O bond-pads on the chip are registered with the corresponding stud-bumps on the substrate. At each stud-bump, the fusible material is caused to fuse with and electrically connect the respective stud-bump to the respective I/O bond-pad on the chip. The method can include forming under-bump metallization (UBM) on each of the I/O bond-pads on the chip before placing the chip on the stud-bumps. The resulting structures provide robust I/O connections and can be fabricated using fewer process steps and using process steps that are compatible with other processes in wafer-fabrication and chip-assembly facilities.

Abstract: A package structure including a first lead, a second lead, an encapsulant, a light-emitting device and an electrostatic discharge (ESD) protection device is provided. The second lead is disposed beside the first lead, and parts of the first lead and the second lead are encapsulated by the encapsulant. The encapsulant has a first cavity and a second cavity. Parts of the first lead and the second lead are exposed by the first cavity and the other parts of the first lead and the second lead are exposed by the second cavity. The light-emitting device is disposed inside the first cavity and electrically connected to the first lead and the second lead. The ESD protection device is disposed inside the second cavity and electrically connected to the first lead and the second lead.

Abstract: The present invention relates to a light-emitting device comprising at least one light-emitting diode, which emits light, and a housing arranged to receive at least a portion of said light. The housing comprises a translucent inorganic material and is provided with at least one recess, which comprises positioning and orientating means. The at least one light-emitting diode is arranged in the at least one recess and is positioned and orientated by said positioning and orientating means, and a translucent inorganic contact layer material is arranged between the at least one light-emitting diode and the housing in the at least one recess to receive at least portion of the light and to connect said light-emitting diode to said housing.

Abstract: A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress.

Abstract: An IGFET that minimizes the effect of the dislocation at the edge of the device region by displacing the lateral edges of the source and drain regions from the adjacent edge of the opening and the dislocation. This minimizes the lateral diffusion of the source and drain impurities and the formation of metal silicides into the dislocation region. The spacing of the lateral edges of the source and drain regions from the adjacent edge of the opening and the dislocation region is produced by providing additional lateral opposed second gate regions or oxide barrier layer extending from the oxide layer into the adjacent regions of the substrate region and the first gate region extending therebetween. Both the first gate region and the two second gate regions or barrier layer are used in the self-aligned processing of the source and drain regions. The first gate region defines the length of the channel, while the two opposed second gate regions or barrier layer define the width of the channel region.

Abstract: A pinned photodiode sensor with gate-controlled SCR switch includes a pinned photodiode and a gate-controlled SCR switch. The SCR switch includes a P-type substrate, an N? doped region, and an N+ doped region formed on the substrate; a P+ doped region formed on the N? doped region; an oxide layer formed on the P substrate, the N? doped region, the N+ doped region, and the P+ doped region; and a gate formed above the P substrate and the N? doped region. The gate includes a P+ doped region and an N+ doped region. During an exposure procedure, a depletion region will not reach the interface between the oxide layer and the substrate, thereby preventing dark current leakage.

Abstract: A foamed bulk metallic glass electrical connection is formed on a substrate of an integrated circuit package. The foamed bulk metallic glass electrical connection exhibits a low modulus that resists cracking during shock and dynamic loading. The foamed bulk metallic glass electrical connection is used as a solder bump for communication between an integrated circuit device and external structures. A process of forming the foamed bulk metallic glass electrical connection includes mixing bulk metallic glass with a blowing agent.

Abstract: A varactor on a substrate is provided. The varactor comprises a bottom electrode, an upper electrode, a first dielectric layer and a conductive layer. The bottom electrode has several doped regions arranged in the substrate as an array with several rows and several columns, wherein the doped regions in adjacent columns are arranged alternatively. The upper electrode is located over the substrate and the upper electrode is composed of several electrode locations and has several openings, wherein each opening exposes the corresponding doped region. Furthermore, each electrode location is surrounded by three doped regions. The first dielectric layer is located between the substrate and the upper electrode. The conductive layer is located over the upper electrode, wherein the conductive layer and the upper electrode are isolated from each other and the conductive layer and the doped regions are electrically connected to each other.

Abstract: An integrated circuit structure is described, and includes a substrate, a contact window, and a Schottky contact metal layer. A heavily doped region and a lightly doped region are formed in the substrate. The contact window is disposed above the heavily doped region, and the Schottky contact metal layer is disposed above the lightly doped region. The Schottky contact metal layer and the substrate form a Schottky diode. The material of the contact window is different from that of the Schottky contact metal layer.

Abstract: The inventive production method of a compound semiconductor light-emitting device (LED)s wafer comprises a step of forming a protective film on the top and/or bottom surface of a compound semiconductor LEDs wafer, where the devices being regularly and periodically arranged with separation zones being disposed; a step of forming separation grooves by means of laser processing in the separation zones of the surface on which the protective film is formed, while a gas is blown onto a laser-irradiated portion; and a step of removing at least a portion of the protective film, which steps are performed in the above sequence.

Abstract: A method and apparatus for a photoinduced electromotive force sensor. The sensor has an active substrate formed of a semi-insulating photoconductor with sufficient carrier trap density to form an effective charge grating and pairs of electrodes disposed on the active substrate, where the sensor is configured to reduce the photovoltaic effect caused by the incident light in the vicinity of the electrodes. The shape or composition of the electrodes may be selected to reduce the photovoltaic effect or the electrodes may be disposed on the substrate to average out the photovoltaic effect arising from each one of the electrodes.

Abstract: A rectifying diode comprising a semiconducting layer, a first electrode, and a second electrode, wherein the width of the region of closest contact between the two electrodes is on the order of the thickness of the semiconducting layer.

Abstract: Provided is a light source that has high reliability and hardly causes conductivity failure between a light emitting device and a conductive land. In an LED light source of the present invention, an LED bare chip is mounted to conductive lands of a substrate, using bumps (55a, 55b). The LED bare chip (D65) is provided with a p-electrode (Lp) and an n-electrode (Ln) on a rear surface. The p-electrode (Lp) is larger in area than the n-electrode (Ln). The p-electrode (Lp) is bonded to a corresponding conductive land via four bumps (55a), whereas the n-electrode (Ln) is bonded to a corresponding conductive land via one bump (55b). A bonded area (Sn) between the n-electrode (Ln) and the bump (55b) is larger than a bonded area (Sp) between the p-electrode (Lp) and one of the bumps (55a).

Abstract: An integrated circuit and fabrication method are presented. The integrated circuit includes a capacitor containing a base electrode, a covering electrode, and a dielectric between the base and covering electrodes. The dielectric contains an oxide of a material contained in the base electrode, which may be produced by anodic oxidation. A peripheral edge of the dielectric is uncovered by the covering electrode. A base layer on the capacitor includes a cutout adjacent to the dielectric. During fabrication, the base layer protects the material of the base electrode that is to be anodically oxidized from chemicals, and also protects the surrounding regions from anodic oxidation. A precision resistor may be fabricated simultaneously with the capacitor.

Abstract: An image sensor and a method of manufacturing the same that includes providing a semiconductor substrate having a photodiode, forming a color filter over the photodiode, forming a micro lens over the color filter and then forming at least one metal layer vertically extending through the microlens at an outer edge thereof.

Abstract: An avalanche photodetector is disclosed. An apparatus according to aspects of the present invention includes a mesa structure defined in a first type of semiconductor. The first type of semiconductor material includes an absorption region optically coupled to receive and absorb an optical beam. The apparatus also includes a planar region proximate to and separate from the mesa structure and defined in a second type of semiconductor material. The planar region includes a multiplication region including a p doped region adjoining an n doped region to create a high electric field in the multiplication region. The high electric field is to multiply charge carriers photo-generated in response to the absorption of the optical beam received in the mesa structure.