Abstract: A module (100) comprises a component (10) and a shielding element (11), which is mounted on a main surface (12) of the component (10) and has a welding contact (13).

Abstract: A nanodevice (1) for a desired function includes a substrate (11), a one-dimensional nanostructure (12), a functional layer (20) having a desired function, a conductive thin film electrode (30), and an insulating layer (40). The one-dimensional nanostructure is operatively extends from the substrate. The functional layer surrounds at least a portion of the one-dimensional nanostructure. The conducting thin film electrode surrounds/encompasses the functional layer. The insulating layer is positioned between the substrate and the conductive thin film electrode, thereby electrically insulating the one from the other. Further, the nanodevice can incorporate one or more functional units 50, each unit including a one-dimensional nanostructure and a respective functional layer. The units may or may not share the same conductive thin film electrode and/or insulating layer.

Abstract: Disclosed herein are embodiments of a semiconductor structure and an associated method of forming the semiconductor structure with shallow trench isolation structures having selectively adjusted reflectance and absorption characteristics in order to ensure uniform temperature changes across a wafer during a rapid thermal anneal and, thereby, limit variations in device performance. Also disclosed are embodiments of another semiconductor structure and an associated method of forming the semiconductor structure with devices having selectively adjusted reflectance and absorption characteristics in order to either selectively vary the performance of individual devices (e.g., to form devices with different threshold voltages (Vt) on the same wafer) and/or to selectively optimize the anneal temperature of individual devices (e.g., to ensure optimal activation temperatures for n-type and p-type dopants during anneals).

Abstract: A light-emitting device has a main semiconductor region formed via an n-type AlInGaN buffer region on a p-type silicon substrate, the latter being sufficiently electroconductive to provide part of the current path through the device. Constituting the primary working part of the LED, the main semiconductor region comprises an n-type GaN layer, an active layer, and a p-type GaN layer, which are successively epitaxially grown in that order on the buffer region. A heterojunction is created between p-type substrate and n-type buffer region. Carrier transportation from substrate to buffer region is expedited by the interface levels of the heterojunction, with a consequent reduction of the drive voltage requirement of the LED.

Abstract: A radiation-emitting component (1) comprising a radiation source, a housing body (6), a radiation exit side (16), an underside (17) which is opposite the radiation exit side (16), a side surface (18) which connects the radiation exit side (16) and the underside (17), and at least one first contact region (2a, 3a). The first contact region (2a, 3a) extends along the side surface (18) and is in the form of a partial region of a carrier (23) that runs outside the housing body (6).

Abstract: A solid-state imaging device includes a pixel array including pixels two-dimensionally arranged in matrix form, with a signal line provided in each column of the arranged pixels, each pixel including a photoelectric conversion element, and a fixing unit fixing the potential of the signal line, which is obtained before the pixel has an operating period, to an intermediate potential between a first power-supply potential and a second power-supply potential.

Abstract: A light-emitting diode is built on a silicon substrate which has been doped with a p-type impurity to possess sufficient conductivity to provide part of the current path through the LED. The p-type silicon substrate has epitaxially grown thereon a buffer region of n-type AlInGaN. Further grown epitaxially on the buffer region is the main semiconductor region of the LED which comprises a lower confining layer of n-type GaN, an active layer for generating light, and an upper confining layer of p-type GaN. In the course of the growth of the buffer region and main semiconductor region there occurs a thermal diffusion of gallium and other Group III elements from the buffer region into the p-type silicon substrate, with the consequent creation of a p-type low-resistance region in the substrate. Interface levels are created across the heterojunction between p-type silicon substrate and n-type buffer region.

Abstract: A thin film transistor (TFT) substrate comprises: a plastic insulation substrate; a first silicon nitride layer with a first refractive index, formed one surface of the plastic insulation substrate; and a TFT comprising a second silicon nitride layer formed with a second refractive index smaller than the first refractive index on the first silicon nitride layer. Thus, the present invention provides a TFT substrate wherein there is reduced a problem in that thin films are lifted from a plastic insulation substrate.

Abstract: The solid-state imaging device of the present invention includes: a floating diffusion capacity unit which is formed on a semiconductor substrate, and is operable to hold signal charges derived from incident light; an amplifier which is operable to convert the signal charges held in the floating diffusion capacity unit into a voltage; the first wire which connects the floating diffusion capacity unit to an input of the amplifier; and a second wire which is made of the same material as the first wire, formed in the same layer as the first wire, arranged around the first wire at least along long sides of the first wire, and electrically insulated from the first wire.

Abstract: A radiation-emitting and/or radiation-receiving semiconductor component comprising a radiation-emitting and/or radiation-receiving semiconductor chip, a molded plastic part which is transparent to an electromagnetic radiation to be emitted and/or received by the semiconductor component and by which the semiconductor chip is at least partially overmolded, and external electrical leads that are electrically connected to electrical contact areas of the semiconductor chip. The molded plastic part is made of a reaction-curing silicone molding compound. A method of making such a semiconductor component is also specified.

Abstract: In manufacturing a semiconductor device, the first gettering layer is formed on the backside of a wafer, and the second gettering layers are then formed on the backside and side surfaces of a chip, allowing these gettering layers to serve as trapping sites against metallic contamination that generated after backside grinding in assembly processes.

Abstract: A photo sensor including a gate, a first insulator, a semiconductor layer, a first electrode pattern layer, a second electrode pattern layer, a second insulator and a transparent electrode is provided. The gate is disposed on the substrate. The first insulator covers the gate and a portion of the substrate. The semiconductor layer is disposed on the first insulator above the gate. Moreover, there is a space between the first electrode pattern layer and the second electrode pattern layer located on the semiconductor layer. The second insulator covers a portion of the semiconductor layer, the first electrode pattern layer and the second electrode pattern layer. The transparent electrode is disposed on the second insulator above the semiconductor layer and corresponds to the first electrode pattern layer. The transparent electrode is electrically connected to the first electrode pattern layer, and a portion of the transparent electrode is within the space.

Abstract: A thin-film device comprises a substrate and a capacitor provided on the substrate. The capacitor incorporates: a lower conductor layer; a dielectric film a portion of which is disposed on the lower conductor layer; and an upper conductor layer disposed on the dielectric film. The lower conductor layer has a top surface, a side surface, and a corner portion formed by the top and side surfaces. The upper conductor layer incorporates an upper electrode portion having a bottom surface opposed to the top surface of the lower conductor layer with the dielectric film disposed in between. When seen from above the upper conductor layer, the periphery of the bottom surface of the upper electrode portion is located inside the periphery of the top surface of the lower conductor layer without touching the periphery of the top surface of the lower conductor layer.

Abstract: A semiconductor device includes a semiconductor substrate having a first conductivity type. The semiconductor substrate includes a first diffusion region having the first conductivity type, a second diffusion region having the first conductivity type, and a channel region between the first diffusion region and the second diffusion region. The device further includes a control gate over the channel region and at least one sub-gate over the first and second diffusion regions.

Abstract: A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The MESFET has a source, a drain and a gate. The gate is between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the gate between the source and the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel layer and electrically coupled to the gate. Related methods are also provided herein.

Abstract: NAND arrays of memory cells are described, as well as methods of forming and using them. Memory cell charge storage devices, such as conductive floating gates, are oriented vertically in trenches, with control gates positioned both in the trenches between charge storage elements and over a horizontal surface between the trenches. Individual charge storage devices are therefore field coupled with two control gates, one on either side.

Abstract: A power semiconductor device having a low loss and a high reliability and a power conversion device using the power semiconductor device are provided. In the power semiconductor device, a plurality of MOS type trench gates are positioned to be spaced by at-least two types of intervals therebetween, a low-resistance floating n+ layer is positioned on a main surface of a semiconductor substrate adjacent to a floating p layer positioned between the adjacent MOS type trench gates having the broad interval to achieve consistency between a low output value and a high breakdown resistance.

Abstract: Embodiments relate to a vertical-type CMOS image sensor, a method of manufacturing the same, and a method of gettering the same, in which source and drain regions are expanded to improve grounding and gettering effects. In embodiments, the vertical-type CMOS image sensor may include a silicon substrate, a first photodiode formed in a prescribed part of the silicon substrate, a first epitaxial layer formed on the silicon substrate, a second photodiode formed on the first epitaxial layer to overlap the first photodiode, a second epitaxial layer formed on the first epitaxial layer, a third photodiode formed on the second epitaxial layer to overlap the second photodiode, and first to third grounded dummy moats formed by implanting impurities into uniform parts on the silicon substrate, the first epitaxial layer, and the second epitaxial layer.

Abstract: A semiconductor device has a trench (42) adjacent to a cell (18). The cell includes source and drain contact regions (26, 28), and a central body (40) of opposite conductivity type. The device is bidirectional and controls current in either direction with a relatively low on-resistance. Preferred embodiments include potential plates (60) that act together with source and drain drift regions (30, 32) to create a RESURF effect.

Abstract: The purpose of the present invention is to provide a nonlinear element with high productivity, which can be driven at low voltage, an element substrate including the nonlinear element, and a liquid crystal display device including the element substrate. A structure of the nonlinear element of the present invention includes a layer formed using a composite material containing an inorganic compound and an organic compound between a first electrode and a second electrode. Further, as the composite material containing the inorganic compound and the organic compound, a composite material, which exhibits nonlinear behavior in both cases of applying forward bias voltage and reverse bias voltage, is used.