Patents Examined by Walter Lindsay
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Patent number: 7425499Abstract: Methods for forming interconnects in blind vias or other types of holes, and microelectronic workpieces having such interconnects. The blind vias can be formed by first removing the bulk of the material from portions of the back side of the workpiece without thinning the entire workpiece. The bulk removal process, for example, can form a first opening that extends to an intermediate depth within the workpiece, but does not extend to the contact surface of the electrically conductive element. After forming the first opening, a second opening is formed from the intermediate depth in the first opening to the contact surface of the conductive element. The second opening has a second width less than the first width of the first opening. This method further includes filling the blind vias with a conductive material and subsequently thinning the workpiece from the exterior side until the cavity is eliminated.Type: GrantFiled: August 24, 2004Date of Patent: September 16, 2008Assignee: Micron Technology, Inc.Inventors: Steven D. Oliver, Kyle K. Kirby, William M. Hiatt
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Patent number: 7424515Abstract: System for deferring the delivery of an e-mail sent by a sender to a receiver through a data transmission network such as Internet wherein a Message Transfer Agent (MTA) associated with the sender is in charge of transmitting over the network any e-mail being sent by the sender. The system comprises a retention server for storing the e-mail whose delivery is to be deferred and an authorization server for giving the retention server the authorization to deliver the stored deferred e-mail to the receiver when predetermined criteria are met. The MTA associated with the sender includes a retention enabling program for sending the deferred e-mail to the retention server when there is an indication in the e-mail that it is to be deferred.Type: GrantFiled: November 3, 2004Date of Patent: September 9, 2008Assignee: International Business Machines CorporationInventors: Jean-Luc Collet, Francois-Xavier Drouet, Gerard Marmigere, Joaquin Picon
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Patent number: 7423286Abstract: The present invention is directed to methods for transferring pre-formed electronic devices, such as transistors, resistors, capacitors, diodes, semiconductors, inductors, conductors, and dielectrics, and segments of materials, such as magnetic materials and crystalline materials onto a variety of receiving substrates using energetic beam transfer methods. Also provided is a consumable intermediate comprising a transfer substrate and a transfer material coated thereon, wherein the transfer material may be comprised of pre-formed electronic devices or magnetic materials and crystalline materials that may be transferred to a variety of receiving substrates. Aspects of the present invention may also be used to form multi-device electronic components such as sensor devices, electro-optical devices, communications devices, transmit-receive modules, and phased arrays using the consumable intermediates and transfer methods described herein.Type: GrantFiled: September 7, 2004Date of Patent: September 9, 2008Assignee: SI2 Technologies, Inc.Inventors: Erik S. Handy, Joseph Michael Kunze, Peter T. Kazlas
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Patent number: 7422914Abstract: A memory test is carried out on semiconductor integrated circuit devices including a semiconductor memory at low cost with efficiency. In a test burn-in system, twenty-four test boards are processed in sequence with time differences, and the test boards are circulated one by one. In this case, the memory test is conducted with the sequence of single board processing: the test is started with a test board in which semiconductor integrated circuit devices have been embedded, and semiconductor integrated circuit devices are discharged, beginning with a test board that has undergone the test.Type: GrantFiled: November 7, 2007Date of Patent: September 9, 2008Assignee: Renesas Technology Corp.Inventors: Yuji Wada, Akira Seito, Masaaki Namba
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Patent number: 7422918Abstract: The present invention relates to a method of making supports for light emitting diodes, wherein rigid substrates are used as supports for light emitting diodes, it being proposed, in particular, to render the substrates more fragile in order to make certain zones of a lower layer of the said substrate more flexible so that the substrate is able to deform in the region of the zones thus made flexible, the deformation then taking place without causing the electrical conduction of a top layer, on which the diodes are disposed, to be broken. In one particular embodiment of the invention it is proposed to provide as many rigid substrate plates as there are support planes in the three-dimensional environment, and to connect these various substrate plates together by means of deformable conductive components disposed in accordance with surface mounted component technology.Type: GrantFiled: November 22, 2005Date of Patent: September 9, 2008Assignee: Valeo VisionInventors: Stéphane Richard, Jean-Marc Nicolai
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Patent number: 7422916Abstract: A method of manufacturing a thin film transistor panel is provided, which includes forming a first signal line on a substrate. The method also includes forming in sequence a first insulating layer and a semiconductor layer on the first signal line. The method further includes patterning the semiconductor layer and the first insulating layer through one photolithography process to form a patterned semiconductor layer and a patterned first insulating layer. The method also includes forming a second signal line on the patterned semiconductor layer and the patterned first insulating layer.Type: GrantFiled: May 10, 2005Date of Patent: September 9, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Bo-Sung Kim, Yong-Uk Lee
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Patent number: 7419887Abstract: An apparatus and method is disclosed for forming a nano structure on a substrate with nano particles. The nano particles are deposited through a nano size pore onto the substrate. A laser beam is directed through a concentrator to focus a nano size laser beam onto the deposited nano particles on the substrate. The apparatus and method is suitable for fabricating patterned conductors, semiconductors and insulators on semiconductor wafers of a nano scale line width by direct nanoscale deposition of materials.Type: GrantFiled: July 26, 2005Date of Patent: September 2, 2008Inventors: Nathaniel R. Quick, Aravinda Kar
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Patent number: 7416910Abstract: An apparatus and method for flexibly suspending a sensing mechanism between a pair of cover plates, including a sensing mechanism formed in a crystalline silicon substrate; a pair of cover plates formed in crystalline silicon substrates; a first plurality of complementary interfaces in fixed relation between the sensing mechanism and a first one of the cover plates; and a second plurality of complementary interfaces flexibly suspended between the sensing mechanism and a second one of the cover plates with one or more of the flexibly suspended interfaces being a complementary male and female interface.Type: GrantFiled: February 6, 2006Date of Patent: August 26, 2008Assignee: Honeywell International Inc.Inventors: Steven A. Foote, Paul H. Collins, J. Christopher Milne
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Patent number: 7417269Abstract: A magnetic sensor apparatus includes a semiconductor substrate and a magnetic impedance device for detecting a magnetic field. The magnetic impedance device is disposed on the substrate. The magnetic sensor apparatus has minimum size and is made with low manufacturing cost. Here, the magnetic impedance device detects a magnetic field in such a manner that impedance of the device is changed in accordance with the magnetic filed when an alternating current is applied to the device and the impedance is measured by an external electric circuit.Type: GrantFiled: November 21, 2003Date of Patent: August 26, 2008Assignee: DENSO CORPORATIONInventors: Kenichi Ao, Yasutoshi Suzuki, Hideya Yamadera, Norikazu Ohta, Hirofumi Funahashi
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Patent number: 7413919Abstract: Methods of manufacturing a diagnostic layer containing an array of sensing elements. The sensing elements, associated wires, and any accompanying circuit elements, are incorporated various layers of a thin, flexible substrate. This substrate can then be affixed to a structure so that the array of sensing elements can analyze the structure in accordance with structural health monitoring techniques. The substrate can also be designed to be incorporated into the body of the structure itself, such as in the case of composite structures.Type: GrantFiled: November 14, 2005Date of Patent: August 19, 2008Assignee: Acellent Technologies, Inc.Inventors: Xinlin Qing, Fu-Kuo Chang
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Patent number: 7407826Abstract: A method for forming a vibrating micromechanical structure having a single crystal silicon (SCS) micromechanical resonator formed using a two-wafer process, including either a Silicon-on-insulator (SOI) or insulating base and resonator wafers, wherein resonator anchors, capacitive air gap, isolation trenches, and alignment marks are micromachined in an active layer of the base wafer; the active layer of the resonator wafer is bonded directly to the active layer of the base wafer; the handle and dielectric layers of the resonator wafer are removed; windows are opened in the active layer of the resonator wafer; masking the active layer of the resonator wafer with photoresist; a SCS resonator is machined in the active layer of the resonator wafer using silicon dry etch micromachining technology; and the photoresist is subsequently dry stripped. A patterned SCS cover is bonded to the resonator wafer resulting in hermetically sealed chip scale wafer level vacuum packaged devices.Type: GrantFiled: December 30, 2005Date of Patent: August 5, 2008Assignee: Honeywell International Inc.Inventors: Ijaz H. Jafri, Galen P. Magendanz
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Patent number: 7407828Abstract: A gate insulation layer with a high dielectric constant for a CMOS image sensor formed by a damascene process. A silicide layer on a gate electrode layer is formed in both a pixel region and a peripheral circuit region, and a silicide layer on a source/drain region is formed only in a peripheral circuit.Type: GrantFiled: December 5, 2005Date of Patent: August 5, 2008Assignee: Dongbu Electronics Co., Ltd.Inventor: Sang-Gi Lee
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Patent number: 7405434Abstract: A nanofluidic channel fabricated in fused silica with an approximately 500 nm square cross section was used to isolate, detect and identify individual quantum dot conjugates. The channel enables the rapid detection of every fluorescent entity in solution. A laser of selected wavelength was used to excite multiple species of quantum dots and organic molecules, and the emission spectra were resolved without significant signal rejection. Quantum dots were then conjugated with organic molecules and detected to demonstrate efficient multicolor detection. PCH was used to analyze coincident detection and to characterize the degree of binding. The use of a small fluidic channel to detect quantum dots as fluorescent labels was shown to be an efficient technique for multiplexed single molecule studies. Detection of single molecule binding events has a variety of applications including high throughput immunoassays.Type: GrantFiled: November 16, 2005Date of Patent: July 29, 2008Assignee: Cornell Research Foundation, Inc.Inventors: Samuel M. Stavis, Joshua B. Edel, Kevan T. Samiee, Harold G. Craighead
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Patent number: 7402893Abstract: According to one embodiment of the invention, a system used in auto-boating includes a tape substrate supported by a boat. The tape substrate includes a pair of lateral edges parallel to one another and each having respective first and second ends, and a pair of longitudinal guide strips parallel to one another. One of the longitudinal guide strips extends between the respective first ends of the pair of lateral edges and the other longitudinal guide strip extends between the respective second ends of the pair of lateral edges. The tape substrate also includes a plurality of die attach regions disposed within the area defined by the pair of lateral edges and the pair of longitudinal guide strips. The system further includes a boat clip coupled to the boat such that the tape substrate is sandwiched between the boat and the boat clip. Each longitudinal guide strip includes a pair of tabs disposed at opposite ends thereof such that each tab extends beyond a respective one of the lateral edges.Type: GrantFiled: November 21, 2003Date of Patent: July 22, 2008Assignee: Texas Instruments IncorporatedInventors: Mark Gerald M. Cruz, Jerry G. Cayabyab
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Patent number: 7402907Abstract: A semiconductor device includes a semiconductor substrate, an actuator provided above the semiconductor substrate to move upwardly, a first electrode layer which is moved by the actuator, and a cap portion provided above the first electrode layer and including a second electrode layer.Type: GrantFiled: October 19, 2005Date of Patent: July 22, 2008Assignee: Kabushiki Kaisha ToshibaInventor: Tatsuya Ohguro
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Patent number: 7399649Abstract: An underlying layer ALY of GaN is formed on a sapphire substrate SSB; a transfer layer TLY of GaN with a bump and dip shaped surface is formed on the underlying layer ALY; a light absorption layer BLY is formed on the bump and dip shaped surface of the transfer layer TLY; and a grown layer 4 of a planarization layer CLY and a structured light-emitting layer DLY having at least an active layer are formed on the light absorption layer BLY. A support substrate 2 is provided on the grown layer 4. The backside of the sapphire substrate SSB is irradiated with light of the second harmonic of YAG laser (wavelength 532 nm) to decompose the light absorption layer BLY and delaminate the sapphire substrate SSB, thereby allowing the planarization layer CLY of a bump and dip shaped surface to be exposed as a light extraction face.Type: GrantFiled: September 27, 2004Date of Patent: July 15, 2008Assignee: Pioneer CorporationInventors: Mamoru Miyachi, Hiroyuki Ota, Yoshinori Kimura, Kiyofumi Chikuma
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Patent number: 7393715Abstract: In an image pickup device, a step of forming an embedded plug includes a step of forming a connecting hole in the insulation film in which the embedded plug is to be formed, a metal layer deposition step of depositing a metal layer on the insulation film in which the connecting hole is formed, thereby covering an interior of the connecting hole and at least a part of an upper surface of the insulation film in a laminating direction thereof, and a metal layer removing step of polishing the upper surface of the insulation film on which the metal layer is deposited thereby removing the metal layer except for the interior of the connecting hole, an etch-back method performed on the embedded plug in at least an insulation film, and a chemical mechanical polishing method performed on the embedded plug in another insulation film.Type: GrantFiled: January 24, 2006Date of Patent: July 1, 2008Assignee: Canon Kabushiki KaishaInventors: Koichi Tazoe, Sakae Hashimoto, Akira Ohtani, Hiroshi Yuzurihara
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Patent number: 7393762Abstract: A method of forming a nanostructure at low temperatures. A substrate that is reactive with one of atomic oxygen and nitrogen is provided. A flux of neutral atoms of at least one of nitrogen and oxygen is generated within a laser-sustained-discharge plasma source and a collimated beam of energetic neutral atoms and molecules is directed from the plasma source onto a surface of the substrate to form the nanostructure. The energetic neutral atoms and molecules in the plasma have an average kinetic energy in a range from about 1 eV to about 5 eV.Type: GrantFiled: November 21, 2006Date of Patent: July 1, 2008Assignee: Los Alamos National Secruity, LLCInventors: Mark Hoffbauer, Alex Mueller
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Patent number: 7393755Abstract: A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.Type: GrantFiled: June 7, 2002Date of Patent: July 1, 2008Assignee: Cadence Design Systems, Inc.Inventors: Taber H. Smith, Vikas Mehrotra, David White
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Patent number: 7390684Abstract: A light emitting apparatus comprising a light emitting device (101) disposed on a supporting body (105), and coating layers ((108, 109) that bind a fluorescent substance that absorbs light emitted by the light emitting device (101) and emits light of a different wavelength and secures the fluorescent substance onto the surface of the light emitting device (101). The coating layers (108, 109) are made of an inorganic material including an oxide and a hydroxide, each containing at least one element selected from the group consisting of Si, Al, Ga, Ti, Ge, P, B, Zr, Y, Sn, Pb and alkali earth metals. Also an adhesive layer (110) is made of the same inorganic material as that of the coating layers (108, 109).Type: GrantFiled: July 27, 2006Date of Patent: June 24, 2008Assignee: Nichia CorporationInventors: Kunihiro Izuno, Kouki Matsumoto, Shinichi Nagahama, Masahiko Sano, Tomoya Yanamoto, Keiji Sakamoto