Abstract: Only a region where TFTs constituting a high-performance circuit will be disposed in a precursor semiconductor film PCS on an insulating substrate GLS with an insulating layer UCL serving as an undercoat is irradiated with a first energy beam LSR so as to be poly-crystallized while growing crystal grains laterally. Further a second rapid thermal treatment is performed all over the panel so as to reduce defects in the crystal grains in a region PSI poly-crystallized by the aforementioned energy beam. Thus, a high-quality polycrystalline semiconductor thin film serving as TFTs for a high-performance circuit and having a high on-current, a low threshold value, a low variation and a sharp leading edge characteristic is obtained.

Abstract: A method for size selection of nanostructures comprising utilizing a gas-expanded liquids (GEL) and controlled pressure to precipitate desired size populations of nanostructures, e.g., monodisperse. The GEL can comprise CO2 antisolvent and an organic solvent. The method can be carried out in an apparatus comprising a first open vessel configured to allow movement of a liquid/particle solution to specific desired locations within the vessel, a second pressure vessel, a location controller for controlling location of the particles and solution within the first vessel, a inlet for addition of antisolvent to the first vessel, and a device for measuring the amount of antisolvent added. Also disclosed is a method for forming nanoparticle thin films comprising utilizing a GEL containing a substrate, pressurizing the solution to precipitate and deposit nanoparticles onto the substrate, removing the solvent thereby leaving a thin nanoparticle film, removing the solvent and antisolvent, and drying the film.

Abstract: In the method of fabricating a metal-insulator-metal (MIM) device, a first electrode of ?-Ta is provided. The Ta of the first electrode is oxidized to form a Ta2O5 layer on the first electrode. A second electrode of ?-Ta is provided on the Ta2O5 layer. Such a device exhibits strong data retention, along with resistance to performance degradation under high temperatures.

Abstract: A method is provided for constructing a nanodevice. The method includes: fabricating an electrode on a substrate; forming a nanogap across the electrode; dispersing a plurality of nanoobjects onto the substrate using electrophoresis; and pushing one of the nanoobjects onto the electrode using a tip of an atomic force microscope, such that the nanoobject lies across the nanogap formed in the electrode. In addition, remaining nanoobjects may also be pushed away from the electrode using the atomic force microscope, thereby completing construction of a nanodevice.

Abstract: This invention relates to a method of fabricating nano-dimensional structures, comprising: depositing at least one deformable material upon a substrate such that the material includes at least one portion; and creating an oxidizable layer located substantially adjacent to the deposited deformable material such that at least a portion of the oxidized portion of the oxidizable layer interacts with the at least one portion of the deformable material to apply a localized pressure upon the at least one portion of the deformable material.

Abstract: A method and article to provide a three-dimensional (3-D) IC wafer process flow. In some embodiments, the method and article include bonding a device layer of a multilayer wafer to a device layer of another multilayer wafer to form a bonded pair of device layers, each of the multilayer wafers including a layer of silicon on a layer of porous silicon (SiOPSi) on a silicon substrate where the device layer is formed in the silicon layer, separating the bonded pair of device layers from one of the silicon substrates by splitting one of the porous silicon layers, and separating the bonded pair of device layers from the remaining silicon substrate by splitting the other one of the porous silicon layers to provide a vertically stacked wafer.

Abstract: A method for manufacturing a memory device having a metal nanocrystal charge storage structure. A substrate is provided and a first layer of dielectric material is grown on the substrate. A layer of metal oxide having a first heat of formation is formed on the first layer of dielectric material. A metal layer having a second heat of formation is formed on the metal oxide layer. The second heat of formation is greater than the first heat of formation. The metal oxide layer and the metal layer are annealed which causes the metal layer to reduce the metal oxide layer to metallic form, which then agglomerates to form metal islands. The metal layer becomes oxidized thereby embedding the metal islands within an oxide layer to form a nanocrystal layer. A control oxide is formed over the nanocrystal layer and a gate electrode is formed on the control oxide.

Abstract: A method for manufacturing a gate electrode structure for preventing abnormal oxidation of a refractory metal due to an oxidation process, includes forming an insulating film on a surface of a semiconductor substrate; forming an impurity diffused polysilicon film on the insulating film; forming an impurity diffusion preventing film on the impurity diffused polysilicon film; forming a refractory metal silicide film on the impurity diffusion preventing film; forming a first nitride film on the refractory metal silicide film; patterning the first nitride film, the refractory metal silicide film and the impurity diffusion preventing film on a gate electrode; forming a first spacer constituted by a second nitride film on side surfaces of the first gate electrode; performing anisotropic etching on the impurity diffused polysilicon film with the first and second nitride films as a mask; and performing an oxidation process.

Abstract: A Carbon NanoTube (CNT) structure includes a substrate, a CNT support layer, and a plurality of CNTs. The CNT support layer is stacked on the substrate and has pores therein. One end of each of the CNTs is attached to portions of the substrate exposed through the pores and each of the CNTs has its lateral sides supported by the CNT support layer. A method of vertically aligning CNTs includes: forming a first conductive substrate; stacking a CNT support layer having pores on the first conductive substrate; and attaching one end of the each of the CNTs to portions of the first conductive substrate exposed through the pores.

Abstract: A method and apparatus for a semiconductor device having a semiconductor device having increased conductive material reliability is described. That method and apparatus comprises forming a conductive path on a substrate. The conductive path made of a first material. A second material is then deposited on the conductive path. Once the second material is deposited on the conductive path, the diffusion of the second material into the conductive path is facilitated. The second material has a predetermined solubility to substantially diffuse to grain boundaries within the first material.

Abstract: An embodiment of the present invention is an interconnect technique. A nanostructure bump is formed on a die. The nanostructure bump has a template defining nano-sized openings and metallic nano-wires extending from the nano-sized openings. The die is attached to a substrate via the nanostructure bump.

Abstract: The invention includes methods of fabricating multiple sets of field effect transistors. In one implementation, an etch stop layer is formed over an insulative capping layer which is formed over a conductive gate layer formed over a substrate. The etch stop layer, the insulative capping layer, and the conductive gate layer are patterned and etched to form a first set of conductive gate constructions over the substrate. A dielectric material is formed and planarized over the first set of gate constructions. Thereafter, the insulative capping layer and the conductive gate layer are patterned and etched to form a second set of conductive gate constructions over the substrate. Other aspects and implementations are contemplated.

Abstract: A metal oxide semiconductor (MOS) transistor having a recessed gate electrode and a fabrication method thereof are provided. The MOS transistor includes a semiconductor substrate and an isolation layer formed in a predetermined region of the semiconductor substrate to define an active region. A channel trench region is disposed within the active region to cross the active region. A gate insulating layer is disposed to cover sidewalls and a bottom of the channel trench region. The MOS transistor has a gate pattern that fills the channel trench region and crosses above the active region. A portion of the sidewall of the gate pattern is recessed at an upper corner of the channel trench region and has a width smaller than the width of the top of the gate pattern and smaller than the width of the channel trench region.

Abstract: A method is disclosed for a multi-zone interference correction processing for a rapid thermal processing (RTP) system. This processing allows for improved calibration/tuning of RTP systems by accounting for zone coupling. The disclosed method includes establishing baseline characteristic data and zone characteristic data, and then using the baseline and zone characteristic data to determine lamp-control parameters, such as temperature offset values, for temperature sensors of the RTP system. The baseline characteristic data includes information regarding baseline heating uniformity of an RTP system. The zone characteristic data is collected for a plurality of heating zones within the heating chamber of the RTP system, each zone being associated with a respective temperature probe. The zone characteristic data is collected based on controlled temperature sensor variations.

Abstract: A substrate processing apparatus includes a reaction chamber with a structure allowing pressure reduction, a shower head for supplying a processing gas into the reaction chamber including a gas diffusion plate in which through holes are formed, and a substrate support for placing a substrate. Each ones of through holes provided in a peripheral region of the gas diffusion plate is formed so that an area of an inlet thereof is larger than an area of an outlet thereof. With use of the substrate processing apparatus, a processing gas can be supplied uniformly in the gas diffusion plate. Therefore, substrate processing such as film deposition and film etching can be uniformly performed.

Abstract: The use of atomic layer deposition (ALD) to form an amorphous dielectric layer of titanium oxide (TiOx) doped with lanthanide elements, such as samarium, europium, gadolinium, holmium, erbium and thulium, produces a reliable structure for use in a variety of electronic devices. The dielectric structure is formed by depositing titanium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing a layer of a lanthanide dopant, and repeating to form a sequentially deposited interleaved structure. Such a dielectric layer may be used as the gate insulator of a MOSFET, as a capacitor dielectric, or as a tunnel gate insulator in flash memories, because the high dielectric constant (high-k) of the film provides the functionality of a thinner silicon dioxide film, and because the reduced leakage current of the dielectric layer when the percentage of the lanthanide element doping is optimized.

Abstract: A method of forming a copper interconnect on a substrate comprises providing a substrate that includes a dielectric layer and a trench etched into the dielectric layer, depositing a barrier layer within the trench, using a palladium immobilization process to form a metal catalyst layer on the barrier layer, activating the metal catalyst layer, and using a vapor deposition process to deposit a copper seed layer onto the metal catalyst layer. The vapor deposition process may include PVD, CVD, or ALD. An electroplating process or an electroless plating process may then be used to deposit a bulk copper layer onto the copper seed layer to fill the trench. A planarization process may follow to form the final interconnect structure.

Abstract: What is proposed here is a method of structuring surfaces of glass-type materials and variants of this method, comprising the following steps of operation: providing a semiconductor substrate, structuring, with the formation of recesses, of at least one surface of the semiconductor substrate, providing a substrate of glass-type material, joining the semiconductor substrate to the glass-type substrate, with a structured surface of the semiconductor substrate being joined to a surface of the glass-type surface in an at least partly overlapping relationship, and heating the substrates so bonded by annealing in a way so as to induce an inflow of the glass-type material into the recesses of the structured surface of the semiconductor substrate. The variants of the method are particularly well suitable for the manufacture of micro-optical lenses and micro-mechanical components such as micro-relays or micro-valves.

Abstract: A method of forming a conductive stud is provided. The method includes providing a substrate which has an upper surface and an opening. The opening exposes a portion of a vertical memory device. A conductive layer is formed over the substrate to fill the opening. A chemical mechanical polishing is performed on the conductive layer to form a conductive stud having an upper surface substantially lower than the upper surface of the substrate.

Abstract: A method of reducing threading dislocation densities in non-polar such as a-{11-20} plane and m-{1-100} plane or semi-polar such as {10-1n} plane III-Nitrides by employing lateral epitaxial overgrowth from sidewalls of etched template material through a patterned mask. The method includes depositing a patterned mask on a template material such as a non-polar or semi polar GaN template, etching the template material down to various depths through openings in the mask, and growing non-polar or semi-polar III-Nitride by coalescing laterally from the tops of the sidewalls before the vertically growing material from the trench bottoms reaches the tops of the sidewalls. The coalesced features grow through the openings of the mask, and grow laterally over the dielectric mask until a fully coalesced continuous film is achieved.