Abstract: A package and method of making a package. In one example, the package includes an at least partially electrically conductive carrier, a passive component mounted on the carrier, and an at least partially electrically conductive connection structure electrically connecting the carrier with the component and comprising spacer particles configured for spacing the carrier with regard to the component.

Abstract: A method for producing a component and a component are disclosed. In an embodiment a method includes providing a substrate, applying a composite of components to the substrate, forming an anchoring layer on the composite of components, attaching a carrier to the anchoring layer, wherein the anchoring layer is disposed between the substrate and the carrier and removing the substrate, wherein the composite of components is divided into a plurality of components by forming a plurality of separating trenches, wherein, after removing the substrate, the components continue to be held on the carrier by the anchoring layer, and wherein the anchoring layer comprises at least one predetermined breaking layer having at least one predetermined breaking position, the predetermined breaking position being laterally surrounded by the separating trenches and—in a plan view of the carrier—being covered by one of the components.

Abstract: A bipolar transistor includes a collector layer, a base layer on the collector layer, and a first elongated emitter mesa on the base layer having a long side and a short side, wherein the long side is parallel with a first direction, and n separate first emitter-contact structures disposed along the first direction on the first elongated emitter mesa, where n is an integer greater than one.

Abstract: Favorable electrical characteristics are provided to a semiconductor device, or a semiconductor device with high reliability is provided. A semiconductor device including a bottom-gate transistor with a metal oxide in a semiconductor layer includes a source region, a drain region, a first region, a second region, and a third region. The first region, the second region, and the third region are each sandwiched between the source region and the drain region along the channel length direction. The second region is sandwiched between the first region and the third region along the channel width direction, the first region and the third region each include the end portion of the metal oxide, and the length of the second region along the channel length direction is shorter than the length of the first region or the length of the third region along the channel length direction.

Abstract: A bidirectional thyristor device includes a semiconductor wafer with a number of layers forming pn junctions. A first main electrode and a first gate electrode are arranged on a first main side of the wafer. A second main electrode and a second gate electrode are arranged on a second main side of the wafer. First emitter shorts penetrate through a first semiconductor layer and second emitter shorts penetrate through a fifth semiconductor layer. In an orthogonal projection onto a plane parallel to the first main side, a first area occupied by the first semiconductor layer and the first emitter shorts overlaps in an overlapping area with a second area occupied by the fifth semiconductor layer and the second emitter shorts. The overlapping area, in which the first area overlaps with the second area, encompasses at least 50% of a total wafer area occupied by the semiconductor wafer.

Abstract: Methods for cutting (e.g., dividing) metal gate structures in semiconductor device structures are provided. A dual layer structure can form sub-metal gate structures in a replacement gate manufacturing processes, in some examples. In an example, a semiconductor device includes a plurality of metal gate structures disposed in an interlayer dielectric (ILD) layer disposed on a substrate, an isolation structure disposed between the metal gate structures, wherein the ILD layer circumscribes a perimeter of the isolation structure, and a dielectric structure disposed between the ILD layer and the isolation structure.

Abstract: Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components.

Abstract: A display device is provided including a display region arranged with a plurality of pixels, and a first sealing region arranged in an exterior periphery part of the display region, the display region includes an individual pixel electrode arranged in each of the plurality of pixels, a common pixel electrode arranged in upper layer of the individual pixel electrode and in succession to the plurality of pixels, and a light emitting layer arranged between the individual pixel electrode and the common pixel electrode, and the first sealing region includes a sealing layer arranged on a lower layer than the common pixel electrode and a region stacked with the common pixel electrode extending from the display region, the stacked region being enclosed by the display region.

Abstract: A multimodal light-emitting OLED microcavity device, comprising: an opaque substrate; a layer with a reflective surface over the substrate; a first electrode over the reflective surface; organic layers for light-emission including a second blue light-emitting layer closer to the reflective surface and a first blue light-emitting layer further from the reflective layer than the second blue light-emitting layer, where the distance between the midpoints of the second and first blue-light emitting layers is L1, and at least one non-blue light-emitting layer; a semi-transparent second electrode with an innermost surface through which light is emitted; wherein the distance L0 between the reflective surface and the innermost surface of the semi-transparent second electrode is constant over the entire light-emitting area; and the ratio L1/L0 is in the range of 0.30-0.40. The multimodal microcavity OLED has increased blue emission and is particularly useful for use as the light source in a microdisplay.

Abstract: A manufacturing method of an isolation structure includes the following steps. A semiconductor substrate is provided. A trench is formed in the semiconductor substrate. A first film forming process is performed to form a first dielectric layer conformally on the semiconductor substrate and conformally in the trench. An annealing process is performed to densify the first dielectric layer and convert the first dielectric layer into a second dielectric layer. A thickness of the second dielectric layer is less than a thickness of the first dielectric layer. A second film forming process is performed after the annealing process to form a third dielectric layer on the second dielectric layer and in the trench. The trench is filled with the second dielectric layer and the third dielectric layer.

Abstract: The present invention provides a semiconductor device including an insulating layer, a conductive layer bonded to one main surface of the insulating layer, a semiconductor element arranged such that the upper surface of the semiconductor element faces a direction same as the one main surface of the insulating layer, an upper electrode provided on the upper surface of the semiconductor element, a wiring member that has one end electrically bonded to the upper electrode of the semiconductor element and has another end electrically bonded to the conductive layer, and has a hollow portion, a first sealing material, and a second sealing material, in which the first sealing material seals at least part of the semiconductor element so as to be in contact with the semiconductor element, and the second sealing material seals the wiring member so as to be in contact with the wiring member.

Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side.

Abstract: An integrated circuit includes a Laterally Diffused MOSFET (LD-MOSFET) located over a semiconductor substrate. The LD-MOSFET transistor includes a dielectric filled trench at a surface of the semiconductor substrate, and a doped region of the semiconductor substrate adjacent the dielectric-filled trench. The doped region and the dielectric-filled trench share an interface that has a terminus at the surface of the semiconductor substrate. An oxide layer is located over the semiconductor substrate, including along a surface of the doped region and along a surface of the dielectric-filled trench. The oxide layer has a first thickness over the dielectric-filled trench and a second greater thickness over the doped region.

Abstract: The present invention comprises: a spool (10); a clamper (22); a torch electrode (31); a high-voltage power source circuit (30); a non-bonding detection circuit (40); a first changeover switch (50) switching a connection between the spool (10) and the high-voltage power source circuit (30) or the non-bonding detection circuit (40); and a relay (53) turning on/off a connection between the clamper (22) and a spool side of the first changeover switch (50), and comprises a control part (60) that sets the first changeover switch (50) to the high-voltage power source circuit side and turns off the relay (53) to generate electric discharge, and that sets the first changeover switch (50) to the non-bonding detection circuit side and turns on the relay (53) to perform non-bonding detection. Due to this configuration, electric corrosion of a wire clamper can be suppressed and non-bonding detection can be carried out with a simple configuration.

Abstract: A light emitting device according to an embodiment includes a body having a recess; a light emitting chip disposed in the recess; and a first dampproof layer sealing the light emitting chip and extended from a surface of the light emitting chip to a bottom of the recess, wherein the light emitting chip includes a wavelength range of 100 nm to 280 nm, and the first dampproof layer includes a fluororesin-based material.

Abstract: A semiconductor memory device has a plurality of gates vertically stacked on a top surface of a substrate, a vertical channel filling a vertical hole that extends vertically through the plurality of gates, and a memory layer in the vertical hole and surrounding the vertical channel. The vertical channel includes a bracket-shaped lower portion filling part of a recess in the top of the substrate and an upper portion extending vertically along the vertical hole and connected to the lower channel. At least one end of an interface between the lower and upper portions of the vertical channel is disposed at a level not than that of the top surface of the substrate.

Abstract: An image sensor device includes a semiconductor substrate, a radiation sensing member, a device layer and a trench isolation. The semiconductor substrate has a front side surface and a back side surface opposite to the front side surface. The radiation sensing member is disposed in a photosensitive region of the semiconductor substrate and extends from the front side surface of the semiconductor substrate. The radiation sensing member includes a semiconductor material with an optical band gap energy smaller than 1.77 eV. The device layer is over the front side surface of the semiconductor substrate and the radiation sensing member. The trench isolation is disposed in an isolation region of the semiconductor substrate and extends from the back side surface of the semiconductor substrate.

Abstract: A semiconductor-on-insulator (e.g., silicon-on-insulator) structure having superior radio frequency device performance, and a method of preparing such a structure, is provided by utilizing a single crystal silicon handle wafer sliced from a float zone grown single crystal silicon ingot.

Abstract: A light emitting diode chip includes: a first conductivity type semiconductor layer; a mesa disposed on a partial region of the first conductivity type semiconductor layer, and including an active layer and a second conductivity type semiconductor layer; a transparent electrode being in ohmic contact with the second conductivity type semiconductor layer; a first current spreader being in ohmic contact with the first conductivity type semiconductor layer; a second current spreader electrically connected to the transparent electrode; an insulation layer covering the mesa, the first current spreader and the second current spreader, and including a distributed Bragg reflector. A lateral distance between the first current spreader and the mesa is larger than a thickness of the insulation layer, and a first side surface of the first current spreader close to the mesa is longer than the second side surface thereof.

Abstract: Methods and devices for a stacked nanofluidic sensor are described. The stacked nanofluidic sensor and methods for forming a nanosheet stack of at least two alternating layers of a first nanosheet material and a second nanosheet material on a substrate. Additionally, a gate structure is formed on the nanosheet stack. Further, nanofluidic channels are formed within the gate structure, including removing each layer of the first nanosheet material within the gate structure to form a channel configured to receive a nanofluidic sample.