Patents Examined by Wensing Kuo
  • Patent number: 9105469
    Abstract: A method and a semiconductor device for incorporating defect mitigation structures are provided. The semiconductor device comprises a substrate, a defect mitigation structure comprising a combination of layers of doped or undoped group IV alloys and metal or non-metal nitrides disposed over the substrate, and a device active layer disposed over the defect mitigation structure. The defect mitigation structure is fabricated by depositing one or more defect mitigation layers comprising a substrate nucleation layer disposed over the substrate, a substrate intermediate layer disposed over the substrate nucleation layer, a substrate top layer disposed over the substrate intermediate layer, a device nucleation layer disposed over the substrate top layer, a device intermediate layer disposed over the device nucleation layer, and a device top layer disposed over the device intermediate layer.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: August 11, 2015
    Assignee: Piquant Research LLC
    Inventors: Zubin P. Patel, Tracy Helen Fung, Jinsong Tang, Wai Lo, Arun Ramamoorthy
  • Patent number: 9081931
    Abstract: A first gate level feature forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second gate level feature forms a gate electrode of a second transistor of the first transistor type. A third gate level feature forms a gate electrode of a second transistor of the second transistor type. The gate electrodes of the second transistors of the first and second transistor types are electrically connected to each other through an electrical connection formed by linear-shaped conductive structures. The gate electrodes of the second transistors of the first and second transistor types are positioned on opposite sides of a gate electrode track along which the gate electrodes of the first transistors of the first and second transistor types are positioned.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 14, 2015
    Assignee: Tela Innovations, Inc.
    Inventors: Scott T. Becker, Jim Mali, Carole Lambert
  • Patent number: 9053939
    Abstract: A heterojunction bipolar transistor (HBT) may include an n-type doped crystalline collector formed in an upper portion of a crystalline silicon substrate layer; a p-type doped crystalline p+Si1-xGex layer, formed above the n-type doped collector, that forms a p-type doped internal base of the HBT; a crystalline silicon cap formed on the p-type doped crystalline p+Si1-xGex layer, in which the crystalline silicon cap includes an n-type impurity and forms an n-type doped emitter of the HBT; and an n-type doped crystalline silicon emitter stack formed within an opening through an insulating layer to an upper surface of the crystalline silicon cap.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: June 9, 2015
    Assignee: International Business Machines Corporation
    Inventors: Thomas N. Adam, David L. Harame, Qizhi Liu, Alexander Reznicek
  • Patent number: 9054211
    Abstract: An FET device structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins.
    Type: Grant
    Filed: July 3, 2012
    Date of Patent: June 9, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni, Ghavam G. Shahidi
  • Patent number: 9034747
    Abstract: A semiconductor device includes a gate insulation layer formed over a substrate and having a high dielectric constant, a gate electrode formed over the gate insulation layer and a work function control layer formed between the substrate and the gate insulation layer and inducing a work function shift of the gate electrode.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: May 19, 2015
    Assignee: SK Hynix Inc.
    Inventors: Yun-Hyuck Ji, Tae-Yoon Kim, Seung-Mi Lee, Woo-Young Park
  • Patent number: 9034757
    Abstract: A method for manufacturing a component having an electrical through-connection is described. The method includes the following steps: providing a semiconductor substrate having a front side and a back side opposite from the front side, producing an insulating trench, which annularly surrounds a contact area, on the front side of the semiconductor substrate, filling the insulating trench with an insulating material, producing an electrical contact structure on the front side of the semiconductor substrate by depositing an electrically conductive material in the contact area, removing the semiconductor material remaining in the contact area on the back side of the semiconductor substrate in order to produce a contact hole which opens up the bottom side of the contact structure, and depositing a metallic material in the contact hole in order to electrically connect the electrical contact structure to the back side of the semiconductor substrate.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: May 19, 2015
    Assignee: ROBERT BOSCH GMBH
    Inventors: Jochen Reinmuth, Jens Frey, Yvonne Bergmann
  • Patent number: 9029999
    Abstract: A semiconductor sensor device is packaged using a footed lid instead of a pre-molded lead frame. A semiconductor sensor die is attached to a first side of a lead frame. The die is then electrically connected to leads of the lead frame. A gel material is dispensed onto the sensor die. The footed lid is attached to the substrate such that the footed lid covers the sensor die and the electrical connections between the die and the lead frame. A molding compound is then formed over the substrate and the footed lid such that the molding compound covers the substrate, the sensor die and the footed lid.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: May 12, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Wai Yew Lo
  • Patent number: 9029925
    Abstract: A solid-state imaging device in which the potential of a signal line, which is obtained before a pixel has an operating period, is fixed to an intermediate potential between a first power-supply potential and a second power-supply potential.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: May 12, 2015
    Assignee: Sony Corporation
    Inventors: Keiji Mabuchi, Toshifumi Wakano, Ken Koseki
  • Patent number: 9023683
    Abstract: A method is provided for forming an epoxy-based planarization layer overlying an organic semiconductor (OSC) film. Generally, the method forms a fluoropolymer passivation layer overlying the OSC layer. A photopatternable adhesion layer is formed overlying the fluoropolymer passivation layer, and patterned. A photopatternable planarization layer, comprising an epoxy-based organic resin, is formed overlying the photopatternable adhesion layer and patterned to expose the fluoropolymer passivation layer. Then, the fluoropolymer passivation layer is plasma etched to expose the OSC layer. More explicitly, the method can be used to fabricate a bottom gate or top gate organic thin-film transistor (OTFT). Top gate and bottom gate OTFT devices are also provided.
    Type: Grant
    Filed: May 13, 2013
    Date of Patent: May 5, 2015
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Karen Nishimura, Lisa Stecker, Themistokles Afentakis, Kurt Ulmer
  • Patent number: 9018681
    Abstract: Consistent with an example embodiment, there is method of manufacturing a bipolar transistor comprising providing a substrate including an active region; depositing a layer stack; forming a base window over the active region in said layer stack; forming at least one pillar in the base window, wherein a part of the pillar is resistant to polishing; depositing an emitter material over the resultant structure, thereby filling said base window; and planarizing the deposited emitter material by polishing. Consistent with another example embodiment, a bipolar transistor may be manufactured according to the afore-mentioned method.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: April 28, 2015
    Assignee: NXP B.V.
    Inventors: Evelyne Gridelet, Tony Vanhoucke, Johannes Josephus Theodorus Marinus Donkers, Hans Mertens, Blandine Duriez
  • Patent number: 9018086
    Abstract: The present invention provides a method of forming a semiconductor device having a metal gate. A substrate is provided and a gate dielectric and a work function metal layer are formed thereon, wherein the work function metal layer is on the gate dielectric layer. Then, a top barrier layer is formed on the work function metal layer. The step of forming the top barrier layer includes increasing a concentration of a boundary protection material in the top barrier layer. Lastly, a metal layer is formed on the top barrier layer. The present invention further provides a semiconductor device having a metal gate.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: April 28, 2015
    Assignee: United Microelectronics Corp.
    Inventors: Chi-Mao Hsu, Hsin-Fu Huang, Chin-Fu Lin, Min-Chuan Tsai, Wei-Yu Chen, Chien-Hao Chen
  • Patent number: 9012289
    Abstract: A semiconductor device and its manufacturing method are disclosed. The semiconductor device comprises a gate, and source and drain regions on opposite sides of the gate, wherein a portion of a gate dielectric layer located above the channel region is thinner than a portion of the gate dielectric layer located at the overlap region of the drain and the gate. The thicker first thickness portion may ensure that the device can endure a higher voltage at the drain to gate region, while the thinner second thickness portion may ensure excellent performance of the device.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: April 21, 2015
    Assignee: Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Jinhua Liu
  • Patent number: 9012277
    Abstract: Generally, the present disclosure is directed to methods for forming dual embedded stressor regions in semiconductor devices such as transistor elements and the like, using in situ doping and substantially diffusionless annealing techniques. One illustrative method disclosed herein includes forming first and second cavities in PMOS and NMOS device regions, respectively, of a semiconductor substrate, and thereafter performing first and second epitaxial deposition processes to form in situ doped first and second embedded material regions in the first and second cavities, respectively. The method further includes, among other things, performing a single heat treating process to activate dopants in the in situ doped first and second embedded material regions.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: April 21, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Ralf Illgen
  • Patent number: 9006904
    Abstract: An electronic package includes a substrate wafer with an interconnect network. A first chip is fixed to a front of the substrate, connected to the interconnect network and encapsulated by a body. A second chip is placed on a back side of the substrate wafer and connected to the interconnect network by back-side connection elements interposed between the back side of the substrate and a front side of the second chip. Front-side connection elements are placed on the front side of the substrate and connected to the interconnect network. The connection elements extend beyond the frontal face of the body. The package may be mounted on a board with an interposed thermally conductive material.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: April 14, 2015
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Dominique Marais, Jacques Chavade, RĂ©mi Brechignac, Eric Saugier, Romain Coffy, Luc Petit
  • Patent number: 9000558
    Abstract: A packaged integrated circuit includes an integrated circuit having a Radio Frequency (RF) passive element formed therein and a wafer level chip scale flip chip package that contains the integrated circuit. The wafer level chip scale flip chip package includes at least one dielectric layer isolating a top metal layer of the integrated circuit and a package signal connection upon the at least one dielectric layer, wherein the package signal connection partially overlays the RF passive element with respect to a surface of the integrated circuit. The RF passive element may be an inductor, a transformer, a capacitor, or another passive element. The package signal connection may be a conductive ball, a conductive bump, a conductive pad, or a conductive spring, for example. A conductive structure may reside upon the at least one dielectric layer to provide shielding to the RF passive element and may include a plurality of conductive elements or a mesh.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: April 7, 2015
    Assignee: Broadcom Corporation
    Inventors: Ali Sarfaraz, Arya Reza Behzad
  • Patent number: 8994195
    Abstract: A microelectronic assembly can include a microelectronic device having device contacts exposed at a surface thereof and an interconnection element having element contacts and having a face adjacent to the microelectronic device. Conductive elements, e.g., wirebonds connect the device contacts with the element contacts and have portions extending in runs above the surface of the microelectronic device. A conductive layer has a conductive surface disposed at at least a substantially uniform distance above or below the plurality of the runs of the conductive elements. In some cases, the conductive material can have first and second dimensions in first and second horizontal directions which are smaller than first and second corresponding dimensions of the microelectronic device. The conductive material is connectable to a source of reference potential so as to achieve a desired impedance for the conductive elements.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: March 31, 2015
    Assignee: Tessera, Inc.
    Inventors: Belgacem Haba, Brian Marcucci
  • Patent number: 8994087
    Abstract: According to one embodiment, a semiconductor device includes a substrate and a first transistor. The substrate has a major surface. The first transistor is provided on the major surface. The first transistor includes a first stacked body, first and second conductive sections, a first gate electrode, and a first gate insulating film. The first stacked body includes first semiconductor layers and first insulating layers alternately stacked. The first semiconductor layers have a side surface. The first conductive section is electrically connected to one of the first semiconductor layers. The second conductive section is apart from the first conductive section and electrically connected to the one of the first semiconductor layers. The first gate electrode is provided between the first and second conductive sections and opposed to the side surface. The first gate insulating film is provided between the first gate electrode and the first semiconductor layers.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: March 31, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masumi Saitoh, Toshinori Numata, Kiwamu Sakuma, Haruka Kusai
  • Patent number: 8981451
    Abstract: A semiconductor memory device includes a substrate, a well region in the substrate, a patterned first dielectric layer on the substrate extending over the well region, a patterned first gate structure on the patterned first dielectric layer, a patterned second dielectric layer on the patterned first gate structure, and a patterned second gate structure on the patterned second dielectric layer. The patterned first gate structure includes a first section extending in a first direction and a second section extending in a second direction orthogonal to the first section, the first section and the second section intersecting each other in a cross pattern. The patterned second gate structure includes at least one of a first section extending in the first direction over the first section of the patterned first gate structure or a second section extending in the second direction over the second section of the patterned first gate structure.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: March 17, 2015
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Cheng-Chi Lin, Shih-Chin Lien, Shyi-Yuan Wu, Chin-Pen Yeh
  • Patent number: 8980718
    Abstract: A method is provided for fabricating a PMOS transistor. The method includes providing a semiconductor substrate, and forming a dummy gate structure at least having a dummy gate, a high-K dielectric layer, and a sidewall spacer surrounding the high-K dielectric layer and the dummy gate on the semiconductor substrate. The method also includes forming a source region and a drain region in the semiconductor substrate at both sides of the dummy gate structure by an ion implantation process, and performing a first annealing process to enhance the ion diffusion. Further, the method includes forming an interlayer dielectric layer leveling with the surface of the dummy gate, and forming a trench by removing the dummy gate. Further, the method also includes performing a second annealing process, and forming a metal gate in the trench.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: March 17, 2015
    Assignee: Semiconductor Manufacturing International Corp.
    Inventor: Yong Chen
  • Patent number: 8975173
    Abstract: A semiconductor device includes buried gates formed over a substrate, storage node contact plugs which are formed over the substrate and include a pillar pattern and a line pattern disposed over the pillar pattern, and a bit line structure which is formed over the substrate and isolates adjacent ones of the storage node contact plugs from each other.
    Type: Grant
    Filed: January 7, 2014
    Date of Patent: March 10, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jong-Han Shin, Bo-Min Park