Abstract: A semiconductor light emitting diode (1, LED), comprising a first and a second electrode (40, 11) for applying a voltage across an active region (4) for generation of light, a light emitting surface (6), and a plurality of photonic crystals (101, 102). Further, at least two photonic crystals (101, 102) of a first and a second type are adapted to extract light from the active region (4) and differ from each other with respect to at least one lattice parameter. Each of said at least two photonic crystals (101, 102) are associated with a respective far field pattern, wherein an arrangement of said plurality of photonic crystals (101, 102) is provided to arrange said at least two photonic crystals (101, 102). In this manner, a far field pattern is created by combining the respective far field patterns associated with each of said at least two photonic crystals (101, 102).

Abstract: A method is provided for applying back contact silver busbars to an aluminum back surface field (BSF) of a solar cell.

Abstract: A semiconductor device including a buried gate and a method for forming the same are disclosed. The semiconductor device includes a buffer layer formed on a surface of a trench in a semiconductor substrate, and a gate electrode configured to partially bury the trench and formed of the same material as in the buffer layer.

Abstract: A semiconductor device has a semiconductor die with bond pads formed on a surface of the semiconductor die. A UBM is formed over the bond pads of the semiconductor die. A fusible layer is formed over the UBM. The fusible layer can be tin or tin alloy. A substrate has bond pads formed on a surface of the substrate. A plurality of stud bumps containing non-fusible material is formed over the bond pads on the substrate. Each stud bump includes a wire having a first end attached to the bond pad of the substrate and second end of uniform height electrically connected to the bond pad of the semiconductor die by reflowing the fusible layer or applying thermal compression bonding. An underfill material is deposited between the semiconductor die and substrate. An encapsulant is deposited over the semiconductor die and substrate.

Abstract: A chip structure includes a semiconductor substrate, an interconnecting metallization structure, a passivation layer, a circuit layer and a bump. The interconnecting metallization structure is over the semiconductor substrate. The passivation layer is over the interconnecting metallization structure. The circuit layer is over the passivation layer. The bump is on the circuit layer, and the bump is unsuited for being processed using a reflow process.

Abstract: Embodiments of a material having low cross-plane thermal conductivity are provided. Preferably, the material is a thermoelectric material. In general, the thermoelectric material is designed to block phonons, which reduces or eliminates heat transport due to lattice vibrations and thus cross-plane thermal conductivity. By reducing the thermal conductivity of the thermoelectric material, a figure-of-merit (ZT) of the thermoelectric material is improved. In one embodiment, the thermoelectric material includes multiple superlattice periods that block, or reflect, multiple phonon wavelengths.

Abstract: In accordance with some embodiments, logical circuits comprising carbon nanotube field effect transistors are disclosed herein.

Abstract: A heat releasing semiconductor package, a method for manufacturing the same, and a display apparatus including the same. The heat releasing semiconductor package includes a film, an electrode pattern formed over the film, a semiconductor device mounted over the electrode pattern, and a first heat releasing layer formed over the semiconductor device including the electrode pattern, the first heat releasing layer including a first adhesive and a first heat releasing material.

Abstract: Methods of fabricating a semiconductor layer or device and said devices are disclosed. The methods include but are not limited to providing a substrate having a crystalline surface with a known lattice parameter (a). The method further includes growing a crystalline semiconductor layer on the crystalline substrate surface by coincident site lattice matched epitaxy, without any buffer layer between the crystalline semiconductor layer and the crystalline surface of the substrate. The crystalline semiconductor layer will be prepared to have a lattice parameter (a?) that is related to the substrate lattice parameter (a). The lattice parameter (a?) maybe related to the lattice parameter (a) by a scaling factor derived from a geometric relationship between the respective crystal lattices.

Abstract: A semiconductor device includes a plurality of semiconductor integrated circuits bonded to a structure body in which a fibrous body is impregnated with an organic resin. The plurality of semiconductor integrated circuits are provided at openings formed in the structure body and each include a photoelectric conversion element, a light-transmitting substrate which has stepped sides and in which the width of the projected section on a first surface side is smaller than that of a second surface, a semiconductor integrated circuit portion provided on the second surface of the light-transmitting substrate, and a chromatic color light-transmitting resin layer which covers the first surface and part of side surfaces of the light-transmitting substrate. The plurality of semiconductor integrated circuits include the chromatic color light-transmitting resin layers of different colors.

Abstract: The invention includes floating body transistor constructions containing U-shaped semiconductor material slices. The U-shapes have a pair of prongs joined to a central portion. Each of the prongs contains a source/drain region of a pair of gatedly-coupled source/drain regions, and the floating bodies of the transistors are within the central portions. The semiconductor material slices can be between front gates and back gates. The floating body transistor constructions can be incorporated into memory arrays, which in turn can be incorporated into electronic systems. The invention also includes methods of forming floating body transistor constructions, and methods of incorporating floating body transistor constructions into memory arrays.

Abstract: A composite substrate (1) comprising a substrate body (2) and a utility layer (31) fixed on the substrate body (2). A planarization layer (4) is arranged between the utility layer (31) and the substrate body (2). A method for producing a composite substrate (1) applies a planarization layer (4) on a provided utility substrate (3). The utility substrate (3) is fixed on a substrate body (2) for the composite substrate (1). The utility substrate (3) is subsequently separated, wherein a utility layer (31) of the utility substrate (3) remains for the composite substrate (1) on the substrate body (2).

Abstract: A semiconductor device includes: a semiconductor substrate having first and second areas; an STI isolation region being made of an isolation trench formed in the semiconductor substrate and an insulating film burying the isolation trench and defining a plurality of active regions in the first and second areas; a first structure formed on an area from the active region in the first area to a nearby STI isolation region and having a first height; and a second structure formed on an area from the active region in the second area to a nearby STI isolation region and having a second height, wherein the surface of the said STI isolation region in the first area is lower than the surface of said STI isolation region in the second area.

Abstract: An LED package includes a substrate, an LED chip, a bounding dam, and a first encapsulation. The substrate includes a first surface and a second surface opposite to the first surface. The LED chip is mounted on the first surface of the substrate. The bounding dam is formed on the first surface of the substrate and surrounds the LED chip. The bounding dam and the substrate cooperatively define a receiving space. The bounding dam is made of thermoset resin. The first encapsulation is formed in the receiving space and encloses the LED chip.

Abstract: A method for fabricating a microelectronic device comprising: a support, an etched stack of thin layers comprising: at least one first block and at least one second block resting on the support, in which at least one drain region and at least one source region, respectively, are capable of being formed, several semiconductor bars connecting a first zone of the first block and another zone of the second block, and able to form a multi-branch transistor channel, or several transistor channels, the device also comprising: a gate surrounding said bars and located between said first block and said second block, the gate being in contact with a first and a second insulating spacer in contact with at least one sidewall of the first block and with at least one sidewall of the second block, respectively, and at least partially separated from the first block and the second block, via said insulating spacers.

Abstract: A semiconductor memory device includes a substrate of a first impurity type, a first well region of a second impurity type in the substrate, the second impurity type being different from the first impurity type, a second well region of the first impurity type in the substrate, a patterned first dielectric layer on the substrate extending over the first and second well regions, a patterned first gate structure on the patterned first dielectric layer, a patterned second dielectric layer on the patterned first gate structure, and a patterned second gate structure on the patterned second dielectric layer. The patterned first gate structure may include a first section extending in a first direction and a second section extending in a second direction orthogonal to the first section, wherein the first section and the second section intersects each other in a cross pattern.

Abstract: A semiconductor device includes an inorganic insulating layer on a semiconductor substrate, a contact plug that extends through the inorganic insulating layer to contact the semiconductor substrate and a stress buffer spacer disposed between the node contact plug and the inorganic insulating layer. The device further includes a thin-film transistor (TFT) disposed on the inorganic insulating layer and having a source/drain region extending along the inorganic insulating layer to contact the contact plug. The device may further include an etch stop layer interposed between the inorganic insulating layer and the semiconductor substrate.

Abstract: In one aspect of the invention, a light emitting device includes an epi layer having multiple layers of semiconductors formed on a substrate, a first electrode and a second electrode having opposite polarities with each other, and electrically coupled to corresponding semiconductor layers, respectively, of the epi layer, and a rod structure formed on the epi layer. The rod structure includes a plurality of rods distanced from each other.

Abstract: A semiconductor light emitting element has a first electrode and a second electrode provided on a semiconductor layer; the first electrode has a first external connector and a first extended portion and second extended portion that extend from the first external connector, the second electrode has a second external connector, and a third extended portion, a fourth extended portion, and a fifth extended portion that extend from the second external connector, the third extended portion extends along the first extended portion and farther outside than the first extended portion, the fourth extended portion extends along the second extended portion and farther outside than the second extended portion, and the fifth extended portion extends an area between the third extended portion and the fourth extended portion to the first external connector side, and the fifth extended portion is either on a line that links a point on the first extended portion at the position closest to the second external connector and a po

Abstract: A method of manufacturing a semiconductor for a transistor that includes forming a precursor layer by coating a surface of an insulation substrate with a precursor solution for an oxide semiconductor, forming an oxide semiconductor by oxidizing a portion of the precursor layer, and removing a remaining precursor layer except for the oxide semiconductor.