Abstract: A thin film transistor, a display device, and a manufacturing method thereof. The thin film transistor includes a control electrode, a semiconductor overlapping the control electrode, and an input electrode and an output electrode disposed on or under the semiconductor and opposite to each other. The semiconductor includes a first portion disposed between the input electrode and the output electrode and having a first crystallinity, and a second portion connected with the first portion, which overlaps the input electrode or the output electrode, and having a second crystallinity. The first crystallinity is higher than the second crystallinity.

Abstract: The present disclosure provides an image sensor semiconductor device. A semiconductor substrate having a first-type conductivity is provided. A plurality of sensor elements is formed in the semiconductor substrate. An isolation feature is formed between the plurality of sensor elements. An ion implantation process is performed to form a doped region having the first-type conductivity substantially underlying the isolation feature using at least two different implant energy.

Abstract: A semiconductor device 10 according to the present invention includes an active layer 14 supported on a substrate 11 and having two channel regions 14c1, 14c2, a source region 14s, a drain region 14d, and an intermediate region 14m formed between the two channel regions 14c1, 14c2; a contact layer 16 having a source contact region 16s, a drain contact region 16d, and an intermediate contact region 16m; a source electrode 18s; a drain electrode 18d; an intermediate electrode 18m; and a gate electrode 12 facing the two channel regions and the intermediate region through a gate insulating film 13 interposed therebetween. An entire portion of the intermediate electrode 18m that is located between the first channel region 14c1 and the second channel region 14c2 overlaps the gate electrode 12 through the intermediate region 14m and the gate insulating film 13.

Abstract: A light emitting diode, comprising: a transparent substrate; a wiring layer; and a semiconductor light emitting element structure part between the transparent substrate and the wiring layer, the semiconductor light emitting element structure part further comprising: a semiconductor light emitting layer; a transparent conductive layer provided on the wiring layer side of the semiconductor light emitting layer; a transparent insulating film; a metal reflection layer; and a first electrode part and a second electrode part provided on the wiring layer side of the transparent insulating film, to be electrically connected to the wiring layer, wherein the first electrode part is electrically connected to the first semiconductor layer via a first contact part which is provided to pass through the transparent insulating film, and the second electrode part is electrically connected to the second semiconductor layer by a second contact part provided to pass through the transparent insulating film, the transparent conduc

Abstract: A single crystal semiconductor layer of a first conduction type is disposed on a surface of a semiconductor substrate. A plurality of trenches are provided in the semiconductor layer to form a plurality of first semiconductor regions of the first conduction type at intervals in a direction parallel to the surface. An epitaxial layer is buried in the plurality of trenches to form a plurality of second semiconductor regions of a second conduction type. The plurality of second semiconductor regions each includes an outer portion with a high impurity concentration formed against an inner wall of the trench, and an inner portion with a low impurity concentration formed inner than the outer portion.

Abstract: A light emitting diode, comprising: a wiring layer; and a semiconductor light emitting element provided on the wiring layer, the semiconductor light emitting element further comprising: a semiconductor light emitting layer; a transparent conductive layer; a metal reflection layer; a transparent insulating film; and a first electrode part and a second electrode part provided on the wiring layer side of the transparent insulating film with an isolating region interposed between them, to be electrically connected to the wiring layer, wherein the first electrode part is electrically connected to the first semiconductor layer by a first contact part, and the second electrode part is electrically connected to the second semiconductor layer by a second contact part which is provided to pass through the transparent insulating film, the transparent conductive layer, the first semiconductor layer, and the active layer.

Abstract: A backside illuminated image sensor includes a substrate, a backside passivation layer disposed on backside of the substrate, and a transparent conductive layer disposed on the backside passivation layer.

Abstract: A method for packing semiconductor components is provided, in which a first side of a first wafer is connected to at least one further wafer, wherein at least one of the wafers has a plurality a semiconductor circuits and wherein trenches are made in the second side of the first wafer opposite to the first side and divide the first wafer into a plurality of parts, which are separated from one another by the trenches, but are connected mechanically to one another by means of the at least one further wafer, and wherein the connecting region between the first wafer and the at least one further wafer has been or will be laterally exposed in the trenches. A coating that covers the connecting region is then applied to the regions of the trenches in which the connecting region is exposed.

Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device, the semiconductor device including: a source trace, a drain trace, and a gate trace placed on a substrate; a transistor which is placed on the drain trace and includes a source pad and a gate pad; insulating films placed between the drain and source traces and between the drain and gate traces on the substrate so as to cover sidewall surfaces of the transistor; a source spray electrode which is placed on the insulating film between the source and drain traces and connects the source pad of the transistor and the source trace; and a gate spray electrode placed on the insulating film between the gate and drain traces and connects the gate pad of the transistor and the gate trace.

Abstract: A thin film transistor having Schottky barrier includes a substrate, a first gate conductive layer formed on the substrate, a first semiconductor layer having a first conductive type formed on the first gate conductive layer, a source conductive layer and a drain conductive layer electrically isolated from each other and positioned on the first semiconductor layer, a second semiconductor layer having a second conductive type formed on the source conductive layer and the drain conductive layer, and a second gate conductive layer formed on the second semiconductor layer. The first conductive type is complementary to the second conductive type.

Abstract: A semiconductor device includes a substrate having a plurality of diffusion regions defined therein to form first and second p-type diffusion regions, and first and second n-type diffusion regions, with each of these diffusion regions electrically connected to a common node. The first p-type active area and the second p-type active area are contiguously formed together. The first n-type active area and the second n-type active area are contiguously formed together. Each of a number of conductive features within a gate electrode level region of the semiconductor device is fabricated from a respective originating rectangular-shaped layout feature. A centerline of each originating rectangular-shaped layout feature is aligned in a parallel manner. A first PMOS transistor gate electrode is electrically connected to a second NMOS transistor gate electrode, and a second PMOS transistor gate electrode is electrically connected to a first NMOS transistor gate electrode.

Abstract: A semiconductor device includes conductive features within a gate electrode level region that are each fabricated from a respective originating rectangular-shaped layout feature having a centerline aligned parallel to a first direction. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along a second gate electrode track. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device.

Abstract: The present invention discloses a nanowire fabrication method and a semiconductor element using a nanowire fabricated thereby. The method of the present invention comprises steps: providing a substrate; sequentially depositing a silicon dioxide layer and a silicon nitride layer on the substrate; forming a patterned photoresist layer on the silicon nitride layer; using the patterned photoresist layer as a mask to etch the silicon nitride layer and the silicon dioxide layer with the substrate partly etched away to form a protrusion; removing the patterned photoresist layer to form an isolation layer; removing the silicon nitride and the silicon dioxide layer, sequentially depositing a dielectric layer and a polysilicon layer; and anisotropically etching the polysilicon layer to form nanowires on a region of the dielectric layer, which is around sidewalls of the protrusion.

Abstract: A semiconductor body (1) comprises a connecting lead (21) for contacting a semiconductor area (2). The conductivity S per unit length of the connecting lead (21) changes from a first value SW to a second value S0. The semiconductor area (2) is electrically conductively connected to the connecting lead (21).

Abstract: A semiconductor device includes a cross-coupled transistor configuration formed by first and second PMOS transistors defined over first and second p-type diffusion regions, and by first and second NMOS transistors defined over first and second n-type diffusion regions, with each diffusion region electrically connected to a common node. Gate electrodes of the PMOS and NMOS transistors are formed by conductive features which extend in only a first parallel direction. The first and second p-type diffusion regions are formed in a spaced apart manner, such that no single line of extent that extends perpendicular to the first parallel direction intersects both the first and second p-type diffusion regions. The first and second n-type diffusion regions are formed in a spaced apart manner, such that no single line of extent that extends perpendicular to the first parallel direction intersects both the first and second n-type diffusion regions.

Abstract: A quadrangle transistor unit includes four transistor units. Each of the four transistor units includes a gate electrode. The gate electrodes of the four transistor units are aligned to four sides of a square. At least two of the four transistor units are connected in parallel.

Abstract: A piezoresistive pressure sensor is especially suitable for measuring smaller pressures and has a small linearity error. The pressure sensor is manufactured from a BESOI wafer having first and second silicon layers and an oxide layer arranged therebetween. The pressure sensor includes, formed from the first silicon layer of the BESOI wafer, an active layer, in which piezoresistive elements are doped, and, formed from the second silicon layer of the BESOI wafer, a membrane carrier, which externally surrounds a cavity in the second silicon layer, via which a membrane forming region of the active layer and an oxide layer associated therewith are exposed, wherein, in an outer edge of the region of the oxide layer exposed by the cavity, a groove is provided surrounding the region.

Abstract: The present invention provides an apparatus for manufacturing a group-III nitride semiconductor layer having high crystallinity. An embodiment of the present invention provides an apparatus for manufacturing a group-III nitride semiconductor layer on a substrate 11 using a sputtering method. The apparatus includes: a chamber 41; a target 47 that is arranged in the chamber 41 and includes a group-III element; a first plasma generating means 51 that generates a first plasma for sputtering the target 47 to supply raw material particles to the substrate 11; a second plasma generating means 52 that generates a second plasma including a nitrogen element; and a control means that controls the first plasma generating means 51 and the second plasma generating means 52 to alternately generate the first plasma and the second plasma in the chamber 41.

Abstract: A method, system, and instrument for automatically measuring transient activity in cells uses image time sequences to identify transients in cells. Preferably, the transient activity is stimulated or provoked in synchronism with acquisition of the image time sequences. A cell mask is applied to each image of an image time sequence in order to localize the transient activity with respect to each cell. Localization enables cell-by-cell analysis of properties of the transient activity.

Abstract: An infrared photodetector including a layer structure of an intermediate layer, and a quantum dot layer having a narrower band gap than the intermediate layer and including a plurality of quantum dots alternately stacked, and detecting photocurrent generated when infrared radiation is applied to the layer structure to thereby detect the infrared radiation, the infrared photodetector further including a first barrier layer provided on one side of the quantum dot layer and having a larger band gap than the intermediate layer; and a second barrier layer provided on the other side of the quantum dot layer and having a larger band gap than the intermediate layer.