Abstract: To form a semiconductor light emitting element provided with three light emitting portions into a monolithic structure, the element of double heterojunction structure has a p-type GaAs semiconductor substrate, an n-type GaAlAs current restriction layer formed with conductive regions arranged at regular intervals, a p-type GaAlAs cladding layer, a p-type GaAlAs active layer, an n-type GaAlAs cladding layer, and two grooves formed extending from the surface of the n-type GaAlAs cladding layer deep through the p-type GaAlAs active layer and between the two adjacent conductive regions. Since the three light emitting portions are formed at precise intervals in a monolithic structure, when mounted on a camera for use with an automatic focusing mechanism, it is possible to measure a distance to a subject in trigonometrical survey without the subject being out of focus.

Abstract: A light emitting semiconductor device which is provided with a first non-single-crystal semiconductor layer, a second non-single-crystal semiconductor layer formed on the first semiconductor layer and a third non-single-crystal semiconductor layer formed on the second semiconductor layer, or a first non-single-crystal semiconductor layer, many second non-single-crystal semiconductor layers formed on the first semiconductor layer and a third non-single-crystal semiconductor layer formed on the first semiconductor layer to cover the second semiconductor layers. The first and second semiconductor layers have either one and the other of p and n conductivity types, respectively. Semiconductors of the first, second and third layers are each doped with a dangling bond and recombination center neutralizer. The semiconductor of the second layer has a smaller energy gap than the semiconductors of the first and third layers.

Abstract: A memory cell structure has a thin insulating oxide barrier layer between an insulating body, such as sapphire, and a conducting layer, such as polysilicon, to prevent photoconduction between the body and the layer. Upper and lower conducting layers form a capacitor with a source and a drain in the lower layer and a gate in the upper layer to isolate the sensitive gate from a substrate during photoconduction. These features help the cell resist a radiation-induced logic state change.

Abstract: A bipolar junction structure comprising a Schottky barrier rectifying contact juxtaposed to a p-n junction having the distribution of p+ diffusions common to a guard ring structure on the Schottky barrier area.

Abstract: A microchannel heat sink used to cool a high power electronic device such as an integrated circuit comprising a plurality of channels in close thermal contact to the integrated circuit and through which a liquid is passed to create either a developing laminar flow or a turbulent flow. The turbulent flow may be either developing or fully developed. The heat sink features a compensation heater surrounding the integrated circuit and heated at the same rate as the integrated circuit to thereby provide a more uniform temperature at the perimeter of the integrated circuit.

Abstract: An integrated semiconductor arrangement of the coupling type between a photodetector D and a light wave guide G.sub.1, operating in a band of given wavelengths, containing on the surface of a semiconductor substrate S of a III-V compound one after the other a confining layer C.sub.0 of III-V compound and a transparent layer C.sub.1 of a III-V compound for the operating wavelengths having an index superior to that of the confining layer, the light waveguide G.sub.1 being realized in layer C.sub.1, and also containing an absorbing layer C.sub.3 of a III-V compound for the operating wavelengths having an index superior to that of the waveguide, in which layer C.sub.3 the photodetector is realized, characterized in that the absorbing layer C.sub.3 is deposited on top of the transparent layer C.sub.1 such that the photodetector is formed on the surface of the light wave guide G.sub.1 and coupled to the latter in parallel with its axis over a given coupling length L.sub.

Abstract: A P-I-N photodetector is fabricated having a first upper light transmitting n.sup.- InP layer overlaying a second light absorbing layer of n.sup.- GaInAs in turn overlaying a substrate of n+InP or N+GaAs, together with p+ ion implant zones formed within the first layer which completely penetrate the first layer and partially penetrate the second layer to form a buried junction within the second layer, the junction being exposed to ambient air. The implants are preferably formed by ion implantation of Be, Cd, Zn or Mg.

Abstract: In an optoelectronic integrated circuit, an electronic device is integrated with an optical device by fabricating the electronic device directly in a doped semiconductor layer of the optical device. The optical devices contemplated for use include at least a region of multiple low-doped or intrinsic quantum well layers; electronic devices include bipolar and field-effect transistors. Resulting integrated circuits exhibit a high degree of planarity.

Abstract: A sensor optimized for detecting infrared radiation is formed by a Schottky barrier photodiode having a corrugated upper surface upon which a thin layer of metal silicide is deposited. The corrugated surface is formed by selective etching of a (100) silicon wafer to expose the (111) crystalline plane.

Abstract: A semiconductor light detecting device comprises a substrate, a first stacked layer of a first conductivity type formed on the substrate by alternately laminating a compound semimetal layer and a compound semiconductor layer repeatedly, a second stacked layer of a second conductivity type formed on the first stacked layer by alternately laminating the compound semimetal layer and the compound semiconductor layer repeatedly, and an isolation region formed by selectively irradiating the first and second stacked layers with an energy beam. A plurality of light detecting elements isolated from each other by the isolation region are formed on the substrate so as to provide the semiconductor light detecting device.

Abstract: An LDD MOSFET structure in which gate sidewall spacers are formed of polycrystalline silicon and electrically shorted to the gate to extend gate control over the LDD region surface oxide and thereby reduce and control interface charge trapping without increasing substrate currents.

Abstract: A light emitting semiconductor device which is provided with a first non-single-crystal semiconductor layer, a second non-single-crystal semiconductor layer formed on the first semiconductor layer and a third non-single-crystal semiconductor layer formed on the second semiconductor layer, or a first non-single-crystal semiconductor layer, many second non-single-crystal semiconductor layers formed on the first semiconductor layer and a third non-single-crystal semiconductor layer formed on the first semiconductor layer to cover the second semiconductor layers. The first and second semiconductor layers have either one or the other of p and n conductivity types, respectively. Semiconductors of the first, second and third layers are each doped with a dangling bond and recombination center neutralizer. The semiconductor of the second layer has a smaller energy gap than the semiconductors of the first and third layers.

Abstract: A semiconductor light emitting device is disclosed which comprises a compound semiconductor substrate, an n type ZnS.sub.x Se.sub.1-x crystal layer (0.ltoreq.x.ltoreq.1) formed on the substrate and containing a Group VII element as a donor impurity, and a p type ZnS.sub.y Se.sub.1-y crystal layer (0.ltoreq.y.ltoreq.1) formed on the n type crystal layer and containing a Group I element as an acceptor impurity, where a pn junction is formed between the n type crystal layer and the p type crystal layer.

Abstract: The sensitivity of an integrated circuit to single-event upsets is decreased by providing a dissiThe U.S. Government has rights in this invention pursuant to Contract No. DE-ACO4-76DP00789 between the Department of Energy and AT&T Technologies, Inc.

Abstract: A bipolar transistor includes a substrate of semiconductor material having an expitaxial body of the semiconductor material on a surface thereof. The semiconductor body has a major surface. A collector region of one conductivity type is in the body at the major surface and a base region of the opposite conductivity type is in the collector region at the major surface and forms with the collector region a collector/base junction which extends to the surface. A plurality of emitter regions of the one conductivity type are in the base region and form with the base region emitter/base junctions which extend to the surface. At least some of the emitter/base junctions are adjacent to but spaced from the collector/base junction at the major surface. A layer of insulating silicon oxide is on the major surface and a layer of conductive polysilicon is on the insulating layer.

Abstract: A semiconductor circuit device includes a semiconductor substrate, a plurality of metal oxide semiconductor (MOS) transistors formed on the semiconductor substrate and a plurality of ground side power source lines formed on the semiconductor substrate. A back gate bias generating circuit is formed between the substrate and the ground side power source lines and supplies a back gate voltage to the substrate. A clamp circuit is provided, which includes an MOS diode formed on the substrate and is connected between the substrate and the ground side power source line. The clamp circuit clamps the potential of the substrate to a predetermined level when the back gate bias generating circuit is not operated.

Abstract: A semiconductor device includes a silicon layer of a first conductivity type, which is disposed on a dielectric substrate and in which at least two zones of a semiconductor circuit element of a second opposite conductivity type and a contact zone having the same conductivity type as, but a higher doping concentration than the silicon layer are provided, which zones adjoin a surface of the silicon layer. According to the invention, the contact zone extends below the zones of the field effect transistor. Thus, it is counteracted that at an interface of the silicon layer and the substrate a channel is formed which shortcircuits the zones. Moreover, the semiconductor device has a constant threshold voltage. This semiconductor device has the additional advantage that it can be manufactured in a very simple manner.

Abstract: Those portions (i.e., the inner lead portions) of the leads of a semiconductor device, which are sealed by a package, are formed with a plurality of depression in at least the surfaces and backs thereof such that the depressions have a smaller diameter at their bottoms than at their surfaces. As a result, both the adhesion strength between a sealer as the package and the inner lead portions of the leads and the mechanical strength of the leads are improved even in a semiconductor device having numerous leads. Moreover, the inner lead portions can be formed in their sides with a number of notches, which can be combined with those depressions to better improve the adhesion strength between the sealant and the inner lead portions of the leads and the mechanical strength of the leads.

Abstract: A double heterostructure light emitting diode comprises a p-active layer, and n and p-cladding layers respectively provided on the both sides of the p-active layer. The p-active layer is doped with p-impurity such that the concentration thereof is distributed therein to be higher in a region proximate to the p-n junction between said p-active and n-cladding layers. As a result, a response time is shortened and light output is increased.

Abstract: Grooves are formed in a single crystal silicon wafer in a pattern to encircle surface areas. Silicon dioxide is placed in the grooves and on the surface and then removed from certain of the areas. Layers of silicon are epitaxially grown only on these areas and their surfaces are oxidized. Polycrystalline silicon is deposited to a thickness greater than that of the epitaxial layers. Both sides of the wafer are ground and polished to produce flat, planar, opposite surfaces; one surface exposing surface areas of the epitaxial layers, the other surface exposing the silicon dioxide in the grooves. The resulting substrate has two types of silicon sections, each of which is electrically isolated from the other by silicon dioxide partitions. One type of section is of silicon of the original wafer, has a surface area in only one surface, and is suitable for the fabrication of low voltage, low power devices therein.