Abstract: A semiconductor P-I-N detector including an intrinsic wafer, a P-doped layer, an N-doped layer, and a boundary layer for reducing the diffusion of dopants into the intrinsic wafer. The boundary layer is positioned between one of the doped regions and the intrinsic wafer. The intrinsic wafer can be composed of CdZnTe or CdTe, the P-doped layer can be composed of ZnTe doped with copper, and the N-doped layer can be composed of CdS doped with indium. The boundary layers is formed of an undoped semiconductor material. The boundary layer can be deposited onto the underlying intrinsic wafer. The doped regions are then typically formed by a deposition process or by doping a section of the deposited boundary layer.

Abstract: Novel metal-alloy interconnections for integrated circuits. The metalalloy interconnections of the present invention comprise a substantial portion of either copper or silver alloyed with a small amount of an additive having a low residual resistivity and solid solubility in either silver or copper such that the resultant electrical resistivity is less than 3&mgr;&OHgr;-cm.

Abstract: There is provided a hetero-junction field effect transistor including a multi-layered structure comprising a buffer layer, a channel layer composed of first semiconductor containing n-type impurity therein, a schottky layer composed of a second semiconductor including a forbidden band having a greater width than a width of a forbidden band of the first semiconductor, an electron donating layer composed of a third semiconductor which includes a forbidden band having a greater width than a width of a forbidden band of the first semiconductor, and further contains n-type impurity therein, a contact layer composed of the first semiconductor or a fourth semiconductor including a forbidden band having a smaller width than a width of a forbidden band of the first semiconductor, a gate electrode formed on an exposed surface of the schottky layer in a recess formed through the electron donating layer and the contact layer, and source and drain electrodes located around the gate electrode.

Abstract: There is provided a solid-state image sensor including (a) a semiconductor layer having a second electrical conductivity, (b) a photoelectric transfer section for converting a light into electric charges, formed on the semiconductor layer, (c) a control transistor formed above the semiconductor layer for controlling operation of the photoelectric transfer section, and (d) a source follower transistor for outputting therethrough a voltage caused by the electric charges, the photoelectric transfer section including (a) a first region having a first electrical conductivity, extending to a gate electrode of the control transistor, and being in electrical connection with a gate electrode of the source follower transistor, and (b) a second region having a first electrical conductivity and formed adjacent to the first region. The solid-state image sensor reduces parasitic capacitance of the photoelectric transfer section to thereby enhance photoelectric transfer efficiency and sensitivity.

Abstract: The object of the invention is to provide a high-efficiency, long-life yet low-cost organic EL device which possesses the merits of both an organic material and an inorganic material. This object is achieved by the provision of an organic EL device which comprises a hole injecting electrode and an electron injecting electrode between which an organic layer having at least a light emitting layer is provided, an inorganic insulating electron transporting layer provided between the light emitting layer and the electron injecting layer, a hole injecting and transporting layer provided between the light emitting layer and the hole injecting electrode, and an organic electron injecting layer provided between the inorganic insulating electron transporting layer and the electron injecting layer.

Abstract: A raised photodetector constructed to define an open channel extending between opposite edges of the photodetector and dimensioned for permitting light from laser to pass therethrough. The photodetector has a light-collecting region disposed in an outward facing wall recessed within the channel for collecting light from the laser.

Abstract: The invention concerns a BI-CMOS process, in which Field-Effect Transistors (FETs) and Bipolar Junction Transistors (BJTs) are manufactured on a common substrate. In several processing steps, FET structures are formed simultaneously with BJT structures. For example, in one step, polysilicon gate electrodes for the FETs and polysilicon emitters for the BJTs are formed simultaneously. In another aspect of the invention, a polysilicon layer is used to reduce channeling which would otherwise occur during an implant step.

Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type formed on the surface of the first semiconductor layer, the energy difference between the bottom of the conductive band and the vacuum level in the second semiconductor layer being smaller than that in the first semiconductor layer, a gate electrode formed above the second semiconductor layer with a gate insulating film interposed therebetween, and a pair of third semiconductor layers of the second conductivity type, being in contact with at least the first semiconductor layer and faced each other in a region of the surface of the first semiconductor layer, so that a channel region is formed under the gate electrode.

Abstract: A method of forming a semiconductor structure having a ferroelectric memory (FEM) gate unit on a substrate of single crystal silicon includes: forming a silicon device area for the FEM gate unit; treating the device area to form area for a source, gate and drain region; depositing an FEM gate unit over the gate junction region, including depositing a lower electrode, depositing a c-axis oriented Pb5Ge3O11 FE layer by Chemical vapor deposition (CVD), and depositing an upper electrode; and depositing an insulating structure about the FEM gate unit. A ferroelectric memory (FEM) cell includes: a single-crystal silicon substrate including an active region having source, gate and drain regions therein; a FEM gate unit including a lower electrode, a c-axis oriented Pb5Ge3O11 FE layer formed by CVD and an upper electrode; an insulating layer, having an upper surface, overlying the junction regions, the FEM gate unit and the substrate; and a source, gate and drain electrode.

Abstract: The electrostatic discharge protection circuit provided by the present invention is an ESD protection circuit with field oxide device, moreover the provided ESD protection circuit uses both PN diode and parasitic bipolar to conduct charger from the input pad of integrated circuit. The equivalent circuit of the invention is equal to the equivalent circuit of conventional FOD kind ESD protection circuit, and the basic structure also is similar to the structure of a conventional ESD protection circuit. The main characteristic of the invention is that deep junction is used to increase junction cross-section area of each junction, especially a deep drain-like junction. In other words, deep junctions are used in the following cases: Drain-like region of field oxide device, diode between VDD and VSS, and diode between the VDD and the pad.

Abstract: A power MOSFET or other semiconductor device contains a layer of silicon combined with germanium to reduce the on-resistance of the device. The proportion of germanium in the layer is typically in the range of 1-40%. To achieve desired characteristics the concentration of germanium in the Si-Ge layer can be uniform, stepped or graded. In many embodiments it is desirable to keep the germanium below the surface of the semiconductor material to prevent germanium atoms from being incorporated into a gate oxide layer. This technique can be used in vertical DMOS and trench-gated MOSFETs, quasi-vertical MOSFETs and lateral MOSFETs, as well as insulated gate bipolar transistors, thyristors, Schottky diodes and conventional bipolar transistors.

Abstract: An ultra-thin highly electrically conductive material is prepared by depositing an amorphous material, substantially free of crystal growth-inducing nuclei and sites, onto a substrate. Deposition is preferably with a plasma deposition reactor, with semiconductor dopants introduced during deposition. Deposition time is preferably adjusted to create an amorphous film of a desired thickness, e.g., 200 Å. After deposition, the amorphous film is annealed preferably with a rapid thermal annealing process for four minutes at 700° C. The annealing triggers the creation of nuclei and subsequent large grain growth in the film, releases energy contained within the amorphous material, and helps drive crystallization and dopant activation. After annealing the material is completely crystallized, and contains large grains whose lateral dimensions can exceed the film thickness by a factor of fifty.

Abstract: A photodetector capable of normal incidence detection over a broad range of long wavelength light signals to efficiently convert infrared light into electrical signals. It is capable of converting long wavelength light signals into electrical signals with direct normal incidence sensitivity without the assistance of light coupling devices or schemes. In the apparatus, stored charged carriers are ejected by photons from quantum dots, then flow over the other barrier and quantum dot layers with the help of an electric field produced with a voltage applied to the device, producing a detectable photovoltage and photocurrent. The photodetector has multiple layers of materials including at least one quantum dot layer between an emitter layer and a collector layer, with a barrier layer between the quantum dot layer and the emitter layer, and another barrier layer between the quantum dot layer and the collector.

Abstract: A lock in pinned photodiode photodetector includes a plurality of output ports which are sequentially enabled. Each time when the output port is enabled is considered to be a different bin of time. A specified pattern is sent, and the output bins are investigated to look for that pattern. The time when the pattern is received indicates the time of flight.

Abstract: Disclosed is an improved field effect transistor (FET) employing both a metal-semiconductor (MES) gate and a metal-insulator-semiconductor (MIS) gate, which FET is particularly useful to provide amplification at microwave frequencies. The use of the MIS gate with appropriate biasing allows the carrier density within a selected portion of the device's channel region to be controlled. The carrier density control increases the breakdown voltage of the FET and enables the FET to be operated with higher maximum channel current and a higher drain to source voltage. As a result, higher output power is provided as compared to prior art MESFET devices of a similar size. Also disclosed is an amplifier circuit including the MES/MIS FET of the preset invention, which amplifier circuit further includes means coupled to the MES/MIS FET for dividing a high frequency input signal to provide a first divided portion and a second divided portion.

Abstract: A power transistor includes a plurality of emitter regions and a plurality of base contacts. In order to decrease base resistance, each of the plurality of emitter regions is adjacent to at least four base contacts. The entire transistor includes multiple emitter regions, e.g., greater than or equal to about 1,000 with no upper limit wherein the actual number of emitter regions is dependent on the desired current carrying capacity. The emitter regions are directly connected in parallel to the high current carrying metal layer of the transistor through vias or metal contact studs. The size of the emitter regions should be made as small as the process design rules will allow in order to allow an increase in the perimeter to area ratio of the emitter region which, for a given current, decreases the peak current density.

Abstract: The present invention discloses a method of forming a metal layer by thermal evaporation or RF reactive sputtering in order to fabricate a light shielding layer for an ion sensitive field effect transistor. The multi-layered construction of the ion sensitive field effect transistor with a metal thin film as a light shielding layer is SnO2/metal/SiO2 or SnO2/metal/Si3N4/SiO2, and is able to lower the effect of light successfully.

Abstract: The use of highly compressively strained In1−xGaxAs quantum wells having a high In content for the detection of light to a wavelength of &lgr;≈2.1 &mgr;m is disclosed. Crystal quality is maintained through strain compensation using tensile strained barriers of InGaAs, InGaP, or InGaAsP. High efficiencies have been achieved in detectors fabricated using this technique. The theoretical cutoff wavelength limit for diodes fabricated using this technique is calculated to be &lgr;˜2.1 &mgr;m. Lattice mismatched layers may be used to transition between compressively strained layers and tensile strained layers to prevent the crystal from breaking up. Multiple quantum wells are formed with multiple periods of strained InGaAs, transition layers and tensile strained layers. These detectors have application in semiconductor, amplifiers, detectors, optical switches, images, etc.

Abstract: According to a first aspect of the present invention, a plurality of PN junctions are formed at the surface of a semiconductor substrate under a belt-like conductive film having a spiral shape which constitutes an inductance device. A reverse bias voltage is applied to the PN junctions, and the surface of the substrate is completely depleted. Since the reverse bias voltage is applied to the PN junctions, even though the impurity density of the surface of the substrate is high and the adjacent PN junctions are separated to a degree, the extension of the depletion layers can be increased and complete depletion of the surface of the substrate can be achieved.

Abstract: A field effect transistor (FET) is formed on a silicon substrate, with a nitride gate insulator layer being deposited on the substrate and an oxide gate insulator layer being deposited on the nitride layer to insulate a gate electrode from source and drain regions in the substrate. The gate material is then removed to establish a gate void, and spacers are deposited on the sides of the void such that only a portion of the oxide layer is covered by the spacers. Then, the unshielded portion of the oxide layer is removed, thus establishing a step between the oxide and nitride layers that overlays the source and drain extensions under the gate void to reduce subsequent capacitive coupling and charge carrier tunneling between the gate and the extensions. The spacers are removed and the gate void is refilled with gate electrode material.