Patents Examined by William A. Powell
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Patent number: 6458709Abstract: A method for fabricating a repair fuse box of a semiconductor device is disclosed. An etching stop polysilicon layer formed at a belt shape in edge portions of a repair fuse box is broken during a repair etching process without substantial departure from prior art methods for fabricating a repair fuse box of a semiconductor device. Thus, it is possible to improve repair yield of the semiconductor device.Type: GrantFiled: January 2, 2001Date of Patent: October 1, 2002Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Eul Rak Kim, Joong Shik Shin
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Patent number: 6458705Abstract: In accordance with the present invention, a method for forming a via-first dual damascene interconnect structure by using gap-filling material whose thickness is easily controlled by a developer is provided. The essential part of the present invention is the application of gap-filling materials such as novolak, PHS, acrylate, methacrylate, and COMA to fill vias. Filling vias with these materials can get a greater planar topography for trench patterning due to its excellent gap-filling capacity, protect the bottom of vias from damage during the trench etch, and prevent the fence problem by using a developer to control its thickness in vias.Type: GrantFiled: June 6, 2001Date of Patent: October 1, 2002Assignee: United Microelectronics Corp.Inventors: Kuei-Chun Hung, Vencent Chang, I-Hsiung Huang, Ya-Hui Chang
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Patent number: 6458710Abstract: A process for defining uniform contact hole openings in an insulator layer, and in a top portion of a conductive layer, has been developed. The process features a series of isotropic and anisotropic, dry etch procedures, used to define an initial contact hole opening in the insulator layer, and in the top portion of the conductive region. The isotropic dry etch procedure results in a tapered contact hole profile for top portion of the initial contact hole opening, while subsequent anisotropic dry etch procedures create a straight walled contact hole profile for the bottom portion of the initial contact hole opening. After removal of the contact hole defining, photoresist shape, a wet etch procedure is used to laterally recess-the insulator layer exposed in the initial contact hole opening creating the final, uniform contact hole opening.Type: GrantFiled: April 9, 2001Date of Patent: October 1, 2002Assignee: ESM LimitedInventor: Hugo Robert Gerard Burke
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Patent number: 6455438Abstract: According to the present invention, a semiconductor device is fabricated by the following processes. First, a film to be etched is formed on a semiconductor substrate. On the film to be etched is formed a resist film. Then, a first pattern group including first patterns having a first size and a second pattern group including second patterns arranged outside of the first pattern group are formed by exposure. The resist film is then developed to form openings in the resist film so that the resultant openings correspond to the first and second patterns, respectively. The openings are then made smaller by annealing the resist film. The aforementioned processes enables openings having substantially the same shape to be formed in the film to be etched.Type: GrantFiled: September 15, 2000Date of Patent: September 24, 2002Assignee: Oki Electric Industry Co., Ltd.Inventors: Azusa Yanagisawa, Koki Muto, Tadashi Nishimuro, Katsuo Oshima, Akira Watanabe, Akihiko Nara, Kouhei Shimoyama, Keisuke Tanaka, Takamitsu Furukawa, Shouzou Kobayashi
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Patent number: 6455333Abstract: A method of stabilizing the DUV resist etch rate for a gate critical dimension, especially for a CD≦75 &mgr;m. More specifically, the present invention provides a method for stabilizing a deep ultraviolet (DUV) resist etch rate by utilizing the directly proportionate relationship between the lateral erosion and a vertical etch rate. The present invention method provides control of lateral erosion of the DUV resist by measuring the vertical etch rate component. The present invention method involves conditioning (seasoning) an etch chamber with a conditioning wafer having a unique stack which results in consistent and stable DUV resist etch rates. The present invention seasoning is applied before processing of a product wafer lot for providing better control of the gate CD targeting, and thereby eliminating a “first wafer” effect.Type: GrantFiled: February 28, 2001Date of Patent: September 24, 2002Assignee: Advanced Micro Devices, Inc.Inventor: Ashok M. Khathuria
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Patent number: 6455433Abstract: A method for forming sidewall spacers with square shoulders on polysilicon gates and the structure formed by the method are disclosed. In the method, a polysilicon gate is first formed on a silicon substrate wherein the gate has a silicon nitride pad on top. A conformal silicon nitride layer is then blanket deposited on top of the structure followed by the deposition of a silicon oxide layer on top of the conformal silicon nitride layer. The silicon oxide layer is then planarized until a top of the conformal silicon nitride layer is exposed. The conformal silicon nitride layer and the silicon nitride pad are then wet etched away to expose the polysilicon gate by using the silicon oxide layer as a mask. After a photoresist layer is coated and etched-back such that only a cavity formed by the silicon oxide layer, the polysilicon gate and the conformal silicon nitride layer is filled with the photoresist, the silicon oxide layer is wet etched away by an etchant such as HF.Type: GrantFiled: March 30, 2001Date of Patent: September 24, 2002Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yao-Chi Chang, Kao-Ming Lu
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Patent number: 6451705Abstract: A method for forming an etched feature in a substrate such as an insulator layer of a semiconductor wafer is provided. In one embodiment, the method includes initially etching a substrate layer using a photoresist or other masking layer to form the etched feature (e.g., opening) to a selected depth, and depositing a self-aligning mask layer for a continued etch of the formed feature. In another embodiment of the method, the self-aligned mask is deposited onto a substrate having an etched opening or other feature, to protect the upper surface and corners of the substrate and sidewalls of the feature while the bottom portion of the opening is cleaned or material at the bottom portion of the opening is removed.Type: GrantFiled: August 31, 2000Date of Patent: September 17, 2002Assignee: Micron Technology, Inc.Inventors: Shane J. Trapp, Kevin G. Donohoe
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Patent number: 6451704Abstract: A new method is provided for the creation of PLDD regions that is aimed at reducing lateral p-type impurity diffusion. The process starts with a silicon substrate on the surface of which gate electrodes have been created. An NLDD implantation is performed self-aligned with the NMOS gate electrode, a layer of oxide (oxide liner) is deposited over the structure over which a layer of nitride is deposited over which a first layer of top oxide is deposited. First gate spacers are formed by etching the first layer of top oxide, stopping on the nitride layer. NS/D and PS/D implantations are performed self-aligned with respectively the NMOS and the PMOS devices, the S/D implantations are annealed. The first gate oxide spacers are removed, a PLDD implantation is performed self-aligned with the PMOS gate electrode. A second layer of top oxide is deposited over the structure and etched to form the second gate spacers on the sidewalls of the NMOS and PMOS gate electrodes.Type: GrantFiled: May 7, 2001Date of Patent: September 17, 2002Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Yelehanka Ramachandramurthy Pradeep, Subrahmanyam Chivukula, Jie Ye, Madhudsudan Mukhopdhyay
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Patent number: 6448094Abstract: A method of detecting an etching depth of a target object includes the steps of irradiating an etching layer of the target object that is being etched in an etching section with light having a plurality of components differing from each other in a wavelength, detecting a plurality of interference light components differing from each other in the wavelength and having an intensity periodically changed by the light components reflected from an upper surface of the etching layer and a surface of the etching section, applying a frequency analysis to these interference light components so as to obtain the frequency of each of these interference wave forms in which the intensity forms the amplitude, calculating an etching rate corresponding to each interference wave form by using the frequency of the interference wave form, and obtaining an etching depth from the etching rate.Type: GrantFiled: January 26, 2001Date of Patent: September 10, 2002Assignee: Tokyo Electron LimitedInventors: Yohei Yamazawa, Yoshihito Ookawa
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Patent number: 6447688Abstract: Disclosed is a novel method for fabricating a stencil mask comprising the formation of an absorber pattern, including an alignment key or target, on the topside of an SOI wafer having a transparent buried insulating layer. The formation of the absorber pattern is followed by the formation of an alignment window from the backside of the SOI wafer using the insulating layer as a lens. The alignment window allows the alignment between the absorber pattern and the frame pattern to be verified, using light passing through the window lens and illuminating the alignment key, before initiating the frame etch, thereby improving the quality and/or throughput of the stencil mask manufacturing process.Type: GrantFiled: April 2, 2001Date of Patent: September 10, 2002Assignee: Hyundai Electronics Industries Co., Ltd.Inventor: Cheol Kyun Kim
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Patent number: 6444589Abstract: An etching method and an etching apparatus for applying an etchant containing nitric acid and hydrofluoric acid to silicon to etch the silicon. The etchant used in etching is recovered, and brought into contact with a gas inert to the etchant, whereby the etchant is regenerated. At least a part of the regenerated etchant is reused in etching.Type: GrantFiled: July 13, 2000Date of Patent: September 3, 2002Assignees: Nisso Engineering Co., Ltd., Disco CorporationInventors: Akira Yoneya, Noriyuki Kobayashi, Nobuhiko Izuta
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Patent number: 6440262Abstract: A resist mark for measuring the accuracy of overlay of a photomask disposed on a semiconductor wafer, includes a first measurement mark having a first opening, formed on the substrate, an intermediate layer formed on the first measurement mark and in the first opening, a frame-shaped second measurement mark formed on the intermediate layer, and a third measurement mark that is spaced from the second measurement mark toward the outside, formed on the intermediate layer. The second measurement mark has a width which is short enough not to be influenced by a deformation caused by the thermal flow phenomenon.Type: GrantFiled: February 4, 2002Date of Patent: August 27, 2002Assignee: Oki Electric Industry Co., Ltd.Inventors: Akiyuki Minami, Satoshi Machida
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Patent number: 6440873Abstract: A post metal etch cleaning method which begins by providing a wafer with an etched metal layer formed thereon, wherein the etched metal layer is covered with a polymer residue. A fluorine based organic acid solvent is used to clean the metal layer, followed by removing the solvent by a physical method. Next, a de-ionized water is applied to flush the metal layer before performing a drying step on the wafer to dry the metal layer.Type: GrantFiled: February 26, 2001Date of Patent: August 27, 2002Assignee: United Microelectronics Corp.Inventors: Chih-Ning Wu, Chan-Lon Yang
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Patent number: 6440870Abstract: The present invention relates to a method of etching tungsten or tungsten nitride in semiconductor structures, and particularly to the etching of gate electrodes which require precise control over the etching process. We have discovered a method of etching tungsten or tungsten nitride which permits precise etch profile control while providing excellent selectivity, of at least 175:1, for example, in favor of etching tungsten or tungsten nitride rather than an adjacent oxide layer. Typically, the oxide is selected from silicon oxide, silicon oxynitride, tantalum pentoxide, zirconium oxide, and combinations thereof. The method appears to be applicable to tungsten or tungsten nitride, whether deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD).Type: GrantFiled: January 5, 2001Date of Patent: August 27, 2002Assignee: Applied Materials, Inc.Inventors: Padmapani Nallan, Hakeem Oluseyi
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Patent number: 6440866Abstract: A general method of the invention is to provide a polymer-hardening precursor piece (such as silicon, carbon, silicon carbide or silicon nitride, but preferably silicon) within the reactor chamber during an etch process with a fluoro-carbon or fluoro-hydrocarbon gas, and to heat the polymer-hardening precursor piece above the polymerization temperature sufficiently to achieve a desired increase in oxide-to-silicon etch selectivity. Generally, this polymer-hardening precursor or silicon piece may be an integral part of the reactor chamber walls and/or ceiling or a separate, expendable and quickly removable piece, and the heating/cooling apparatus may be of any suitable type including apparatus which conductively or remotely heats the silicon piece.Type: GrantFiled: June 16, 2000Date of Patent: August 27, 2002Assignee: Applied Materials, Inc.Inventors: Kenneth S. Collins, Michael Rice, David W. Groechel, Gerald Zheyao Yin, Jon Mohn, Craig A. Roderick, Douglas Buchberger, Chan-Lon Yang, Yuen-Kui Wong, Jeffrey Marks, Peter Keswick
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Patent number: 6440869Abstract: The present invention discloses the method of forming the bottom electrode with HSG (hemispherical grain) layer on substrate, said substrate comprising a word line and an active region, said method comprising the steps of: depositing a confomal etch stop layer on said active region and said word line; forming a dielectric layer on said etch stop layer with planar top surface; forming a contact hole in said. dielectric layer and said etch stop layer to expose portions of said active region and said word line; depositing a first conductive layer on the surface of the contact hole; forming a hemishperical grain (HSG) layer on said first conductive layer; and removing said dielectric layer.Type: GrantFiled: June 26, 2000Date of Patent: August 27, 2002Assignee: Vanguard International Semiconductor CorporationInventor: Horng-Huei Tseng
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Patent number: 6440872Abstract: A process of forming a hybrid memory cell which is scalable to a minimum feature size, F, of about 60 nm at an operating voltage of Vblh of about 1.5 V and substantially free of floating-well effects.Type: GrantFiled: November 3, 2000Date of Patent: August 27, 2002Assignee: International Business Machines CorporationInventors: Jack A. Mandelman, Ramachandra Divakaruni, Carl J. Radens, Stephan Kudelka
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Patent number: 6440864Abstract: A substrate cleaning method comprises exposing a substrate 30 to an energized process gas to remove residue 60 and resist material 50 from the substrate 30. In one version, the process gas comprises cleaning gas, such as an oxygen-containing gas, and an additive gas, such as NH3. In one version, the process gas is introduced to remove residue 60 and resist material 50 from the substrate and to remove residue from surfaces in the process chamber 75.Type: GrantFiled: June 30, 2000Date of Patent: August 27, 2002Assignee: Applied Materials Inc.Inventors: Thomas J. Kropewnicki, Jeremiah T. Pender, Henry Fong, Charles Peter Auglis, Raymond Hung, Hongqing Shan
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Patent number: 6436834Abstract: The invention provides a chemical-mechanical abrasive composition for use in semiconductor processing, which comprises an aqueous medium, an abrasive, and an abrasion accelerator. The abrasion accelerator mainly functions to enhance the removal rate of the substances to be removed, and selected from the compounds of the following formula, the acid-addition salts thereof, or mixtures of two or more of the foregoing compounds and salts: wherein X and Y are independently lone-pair electrons containing atoms or atomic groups; and R1 and R2 are independently H, alky, amino, aminoalkyl, or alkoxy. The chemical-mechanical abrasive composition of the invention may optionally comprise an acidic component and/or a salt thereof, so as to further enhance the abrasion rate. The invention further provides a method of using the above chemical-mechanical abrasive composition for polishing the surface of a semiconductor wafer.Type: GrantFiled: July 7, 2000Date of Patent: August 20, 2002Assignee: Eternal Chemical Co., Ltd.Inventors: Tsung-Ho Lee, Kang-Hua Lee, Tsui-Ping Yeh
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Patent number: 6436832Abstract: High through-put CMP is achieved by the application of a cleaning composition on to an exposed surface of a metal layer prior to polishing the bulk metal layer. Embodiments of the present invention include applying an aqueous composition containing citric acid and ammonium hydroxide in deionized water to remove a native oxide film that forms on a copper containing layer and then polishing the copper containing layer to substantially planarize the metal layer.Type: GrantFiled: May 23, 2000Date of Patent: August 20, 2002Assignee: Applied Materials, IncInventors: Yutao Ma, Juilung Li, Fred C. Redeker, Tse-Yong Yao, Rajeev Bajaj