Patents Examined by William Bunch
  • Patent number: 5123847
    Abstract: An improved method of manufacturing active matrix display backplanes with thin film transistors thereon and a drive scheme therefor. A refractory metal covers the indium tin oxide (ITO) layer, patterned to form a gate electrode for the transistors and to protect the pixel pad ITO during formation of the transistors. To reduce shorts and capacitance between the gate and the source or the drain, an intermetal dielectric is patterned to form a central portion over a planar portion of the gate region and to cover any exposed gate edges.
    Type: Grant
    Filed: January 16, 1990
    Date of Patent: June 23, 1992
    Inventors: Scott H. Holmberg, Richard A. Flasck
  • Patent number: 5120676
    Abstract: A MOCVD process for depositing an arsenic-containing film or a phosphorous-containing film utilizing a diprimary phosphine or arsine or an unsaturated hydrocarbon phosphine or arsine.
    Type: Grant
    Filed: March 23, 1990
    Date of Patent: June 9, 1992
    Assignee: CVD Incorporated
    Inventors: Andreas A. Melas, Ravi K. Kanjolia, Ben C. Hui
  • Patent number: 5114877
    Abstract: In situ removal of selected or patterned portions of quantum well layers is accomplished by photo induced evaporation enhancement to form quantum wire and multiple quantum wires in a semiconductor laser structure.
    Type: Grant
    Filed: January 8, 1991
    Date of Patent: May 19, 1992
    Assignee: Xerox Corporation
    Inventors: Thomas L. Paoli, John E. Epler
  • Patent number: 5087587
    Abstract: A window semiconductor laser device comprising a stripe-channeled substrate, an active layer for laser oscillation and a cladding layer disposed under the active layer, wherein the surface of the active layer is flat and the thickness of the portion of the active layer corresponding to the striped channel of said substrate in each of the window regions in the vicinity of the facets is thinner than that of the portion of the active corresponding to the striped channel of said substrate in the stimulated region positioned between the window regions.
    Type: Grant
    Filed: February 9, 1987
    Date of Patent: February 11, 1992
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Taiji Morimoto, Shigeki Maei, Hiroshi Hayashi, Saburo Yamamoto
  • Patent number: 5082799
    Abstract: A semiconductor laser having a high modulation bandwidth is made by utilizing an InGaAsP cap layer and an InGaAsP active layer of different crystal structure. Channels are anisotropically etched through the cap, cladding and active layers and partially through the buffer layer. The active and cap layers a laterally etched and a semi-insulating material is overlaid the sidewalls. A further etching leaves a thin wall of the semi-insulating material surrounding the active layer. 1.3 .mu.m InGaAsP lasers with 3 dB bandwidths of 24 GHz and intrinsic resonance frequencies in excess of 22 GHz have been successfully fabricated. This is the highest bandwidth ever reported for a semiconductor laser, and the highest resonance frequency for InGaAsP lasers. Excellent modulation efficiencies are observed to high frequencies.
    Type: Grant
    Filed: September 14, 1990
    Date of Patent: January 21, 1992
    Assignee: GTE Laboratories Incorporated
    Inventors: Roger P. Holmstrom, Edmund Meland, William Powazinik
  • Patent number: 5079184
    Abstract: A magnesium-doped p-type III-V Group compound semiconductor layer can be formed by metal organic chemical vapor deposition, by reacting, in a vapor phase, at least one compound of a Group III element with at least one compound of a Group V element, in the presence of an adduct of an organic magnesium compound with another compound as a doping source of magnesium.
    Type: Grant
    Filed: June 15, 1990
    Date of Patent: January 7, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ako Hatano, Toshihide Izumiya, Yasuo Ohba
  • Patent number: 5079187
    Abstract: A method for processing semiconductor material for annealing or circuitizing purposes, includes establishing a high intensity light which is controlled at a high repetition rate, and exposing it toward the surface of the semiconductor material to process it in an improved manner. The high speed light is directed transversely to the surface of the material to be processed, only to a shallow depth.
    Type: Grant
    Filed: May 4, 1989
    Date of Patent: January 7, 1992
    Assignee: The Regents of the University of California
    Inventors: John F. Asmus, Ralph H. Lovberg
  • Patent number: 5076860
    Abstract: A compound semiconductor material includes Ga.sub.x Al.sub.1-x N (wherein 0.ltoreq.x.ltoreq.1) containing B and P and having a zinc blend type crystal structure. A compound semiconductor element includes Ga.sub.x Al.sub.1-x N (wherein 0.ltoreq.x.ltoreq.1) layer having a zinc blend type crystal structure. A method of manufacturing a compound semiconductor element includes the step of sequentially forming a BP layer and a Ga.sub.x Al.sub.1-x N (wherein 0.ltoreq.x.ltoreq.1) layer on a substrate so as to form a heterojunction by using a metal organic chemical vapor deposition apparatus having a plurality of reaction regions, and moving the substrate between the plurality of reaction regions.
    Type: Grant
    Filed: September 29, 1989
    Date of Patent: December 31, 1991
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuo Ohba, Toshihide Izumiya, Ako Hatano
  • Patent number: 5075239
    Abstract: A method of making monolithic integrated optoelectronic modules in which passivation and electric isolation of the individual components are achieved with an epitaxially deposited, semi-insulating (SI) indium phosphide layer. Instead of a semi-insulating substrate, a conducting substrate can therefore be used, which results in a better lattice structure of the deposited layers.
    Type: Grant
    Filed: March 2, 1990
    Date of Patent: December 24, 1991
    Assignee: Alcatel N.V.
    Inventor: Franz-Josef Tegude
  • Patent number: 5070034
    Abstract: A semiconductor memory device is provided with memory cells each having a capacitor for accumulating an electric charge and a transistor for charging and discharging the capacitor. The memory device comprises a substrate, an insulator layer formed thereon and a monocrystalline semiconductor layer formed thereon. The capacitor is composed of said monocrystalline semiconductor layer, the insulator layer and the substrate while the transistor is formed in the monocrystalline semiconductor layer.
    Type: Grant
    Filed: September 28, 1990
    Date of Patent: December 3, 1991
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tamotsu Satoh, Takao Yonehara, Yoshio Nakamura
  • Patent number: 5068204
    Abstract: A blue light emitting diode which has a multiple layer structure and is grown on a semiconductor crystalline substrate, wherein zinc of a group II element of the periodic table, lithium, sodium, or potassium of group VI elements are used. These elements and their compounds are used as impurities to be introduced into the construction when it is at the condition of vapor growing. A blue light emitting diode has a pair of Ohmic electrodes, an n-type semiconductor layer and a p-type semiconductor layer. These layers are grown from a vapor phase on the substrate and sandwiched between the electrodes.
    Type: Grant
    Filed: March 25, 1988
    Date of Patent: November 26, 1991
    Assignee: Misawa Co. Ltd.
    Inventors: Hiroshi Kukimoto, Iwao Mitsuishi, Takashi Yasuda
  • Patent number: 5066610
    Abstract: Wetting of encapsulated silicon-on-insulator (SOI) films during a zone-melting recrystallization (ZMR) process is enhanced by a high temperature anneal of the SOI structure in a reactive nitrogen-containing ambient to introduce nitrogen atoms to the polysilicon/silicon dioxide cap interface. The technique is not only more effective in present in cap fracture and enhancing crystal quality but is also susceptible to batch processing with noncritical parameters in a highly efficient, uniform manner. Preferably, the cap is exposed to 100% ammonia at 1100.degree. C. for one to three hours followed by a pure oxygen purge for twenty minutes. The ammonia atmosphere is reintroduced at the same temperature for another one to three hour period before ZMR. The process is believed to result in less than a half monolayer of nitrogen at the interior cap interface thereby significantly lowering the contact angle and improving the wetting character of the SOI structure.
    Type: Grant
    Filed: September 22, 1989
    Date of Patent: November 19, 1991
    Assignee: Massachusetts Institute of Technology
    Inventors: Chenson K. Chen, Bor-Yeu Tsaur
  • Patent number: 5064779
    Abstract: In a method of manufacturing a poly-Si film, silicon is deposited on a substrate by means of a thermal decomposition of a feed gas and plasma generation. The method comprises the step of arranging said substrate within a reaction apparatus, the step of introducing into said reaction apparatus a feed gas containing a silane-series gas for thermal decomposition of the feed gas at 500.degree. to 800.degree. C., and the step of generating plasma within the feed gas by applying power for generating the plasma simultaneously with the thermal decomposition, said power for plasma generation being controlled at a level lower than the power applied for forming a poly-Si film oriented in the <110> direction, so as to form a poly-Si film substantially oriented in the <100> direction and having a smooth surface.
    Type: Grant
    Filed: January 31, 1990
    Date of Patent: November 12, 1991
    Assignee: President of Kanazawa University
    Inventor: Seiichi Hasegawa
  • Patent number: 5063166
    Abstract: A low dislocation density semiconductor device includes a first semiconductor layer of a III-V or II-VI semiconductor compound and alloying atoms on a non-metal substrate. The semiconductor compound usually has a large dislocation density. A predetermined position of the alloying atoms in the compound lattice structure can substantially reduce the compound dislocation density. Energy is applied to the alloying atoms so they are at the predetermined positions. The number of alloying atoms causes the semiconductor compound solubility limit to be exceeded. The layer is formed on a substrate of the III-V or II-VI semiconductor, such as gallium arsenide or another semiconductor, such as silicon or on an insulator such as sapphire. In the latter cases, the layer is formed on an intermediate layer having a lattice constant between that of the substrate and semiconductor compound.
    Type: Grant
    Filed: April 9, 1990
    Date of Patent: November 5, 1991
    Assignee: SRI International
    Inventors: John B. Mooney, Arden Sher
  • Patent number: 5061643
    Abstract: A method of growing a semiconductor thin film by MOCVD including doping with a doping gas producing a carrier concentration regulated by the decomposition speed of the doping gas, selectively irradiating the doping gas with ultraviolet light before the doping gas reaches the growing film, whereby the decomposition speed of the doping gas is increased.
    Type: Grant
    Filed: December 27, 1989
    Date of Patent: October 29, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Tetsuya Yagi
  • Patent number: 5061652
    Abstract: A semiconductor structure including a doped semiconductor substrate defining a surface. A buffer layer of epitaxial semiconductor material overlies the substrate surface, the buffer layer having a relatively higher dopant concentration than the substrate and being virtually free from oxygen precipitation. A layer of intrinsic semiconductor material overlies the buffer layer, and a device layer of epitaxial semiconductor material is situated on the intrinsic layer. The device layer is formed to have a relatively lower dopant concentration than the first layer. Isolation regions extend from a surface of the device layer into the buffer layer for forming an electrically isolated device region in the device layer. At least one active device is formed in the isolated device region.
    Type: Grant
    Filed: January 23, 1990
    Date of Patent: October 29, 1991
    Assignee: International Business Machines Corporation
    Inventors: Robert E. Bendernagel, Kyong-Min Kim, Victor J. Silvestri, Pavel Smetana, Thomas H. Strudwick, William H. White
  • Patent number: 5057442
    Abstract: A light-emitting diode prepared by a new process is disclosed. The light-emitting diode has compound semiconductor epitaxial layers composed of GaAs.sub.1-x P.sub.x (0.ltoreq.x.ltoreq.1) on a compound semiconductor GaP single-crystal substrate, and has a light-emitting layer provided with a p-n junction formed in the surface layer region of the epitaxial layers. The diode is characterized in that it has a total maximum thickness of the epitaxial layers 20 to 40 .mu.m.The process for preparing the diode is characterized in that the process can determine a required maximum thickness of the compound semiconductor epitaxial layers by presuming light output power from the thickness of the epitaxial layers based on the following equation:L=exp(Ax.sub.0 +B)+Cwhere A, B and C are definite values obtained from experiments conducted, L is light output power and x.sub.0 is the total thickness of the epitaxial layers.
    Type: Grant
    Filed: May 30, 1990
    Date of Patent: October 15, 1991
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventor: Hitoshi Habuka
  • Patent number: 5055422
    Abstract: The present invention relates to processes for the construction of semiconductor lasers.The process according to the invention is essentially characterized in that it consists in forming a layer 1 of a laser semiconductor active medium, in forming an optical cavity 2 associated with this layer, in disposing, on at least a part of the surface of the layer, first 6 and second 7 layers of materials of impurities of opposite polarities, in causing diffusion into the active medium of at least a part of the two materials of impurities to form, in the first layer, a cylinder 8 axis substantially parallel to the axis of the optical cavity and formed of two semi-cylindrical half-shells 9, 10 of diffused impurities of opposite polarities, and in connecting two conductors 12 of the electrical energy respectively to the two half-shells.Application to the construction of a plurality of laser diodes on one and the same support substrate, to create a homogeneous and dense single laser beam.
    Type: Grant
    Filed: July 24, 1990
    Date of Patent: October 8, 1991
    Assignee: Thomson-CSF
    Inventors: Claude Weisbuch, Baudouin De Cremoux, Jean P. Pocholle
  • Patent number: 5048163
    Abstract: A system for processing the surface of semiconductor material for annealing and etching purposes. The system established a high intensity ultraviolet light which is repetitively pulsed to rapidly raise the surface temperature of the semiconductor material to a predetermined temperature for either etching or annealing purposes.
    Type: Grant
    Filed: May 4, 1989
    Date of Patent: September 17, 1991
    Inventors: John F. Asmus, Ralph H. Lovberg
  • Patent number: 5049523
    Abstract: In a gaseous glow-discharge process for coating a substrate with semiconductor material, a variable electric field in the region of the substrate and the pressure of the gaseous material are controlled to produce a uniform coating having useful semiconducting properties. Electrodes having concave and cylindrical configurations are used to produce a spacially varying electric field. Twin electrodes are used to enable the use of an AC power supply and collect a substantial part of the coating on the substrate. Solid semiconductor material is evaporated and sputtered into the glow discharge to control the discharge and improve the coating. Schottky barrier and solar cell structures are fabricated from the semiconductor coating. Activated nitrogen species is used to increase the barrier height of Schottky barriers.
    Type: Grant
    Filed: August 16, 1989
    Date of Patent: September 17, 1991
    Assignee: Plasma Physics Corp.
    Inventor: John H. Coleman