Abstract: An improved resistor for use in MOS integrated circuits. An opening is formed in an insulative layer which separates two conductive regions. A plasma enhanced chemical vapor deposition of passivation material such as silicon-rich silcon nitride is deposited in the window, contacting both conductive regions and providing resistance in a vertical direction between these regions.A subsequent annealing process involving controlled temperatures and cycle times provides for determining desired resistive values from an equivalent deposition process. Further, a barrier metal layer may be formed between the vertical resistor and the second conductive region.

Abstract: With an increase of integration density in an integrated circuit, the channel length of MIS FET becomes shorter and shorter, which causes a hot carrier effect. To solve the problem, the doping profile of source/drain regions and doping amount must be precisely controlled such that a strong electric field is not generated in a transition region from channel to drain. To obtain this objective, the present invention discloses a method, in which reflowed sidewalls of doped silicate glass having a gentle slope are formed on both sides of a gate electrode, and the gate electrode and the sidewalls thus formed are used as a mask for ion implantation. The depth of ion implantation and the doping amount change gradually from the channel region to the drain region avoiding a generation of the strong electric field and thus alleviates the short channel trouble.

Abstract: As a process for fabricating uniform patterns fine enough to produce a quantum size effect, the use of electron halography is proposed. Disclosed examples employing a process are methods of manufacturing a semiconductors laser whose threshold current is approximately 1 mA, and a permeable transistor and bistable device whose response rates are 100 GHz.

Abstract: A method of manufacturing a semiconductor device including the step of depositing from the vapor layers on a substrate in the chamber of a reactor in which a vector gas and a reactant gas are introduced, characterized in that the vector gas and the reactant gas are introduced into the chamber of the reactor by means of a system of three coaxial tubes, the first of which (the inner tube) has a diameter smaller than that of the second tube (the intermediate tube), which in turn has a diameter smaller than that of the third tube (the outer tube), the first ends of these tube being independent, but the second ends thereof situated in the proximity of each other cooperating with each other so as to form a valve controlling the introduction of the reactant gas into the hot zone of the chamber of the reactor mixed with a vector gas, these tubes being disposed in such a manner that: the said second end of the inner tube merges into the intermediate tube, the said second end of the intermediate tube provided with a re

Abstract: A fully self-aligned polycrystalline silicon emitter bipolar transistor. Self-alignment of the p.sup.+ base contact (12) is achieved by using oxidized sidewalls (8) (sidewall spacers) of the emitter mesa (7) as part of the p.sup.+ base contact implantation mask. Collector contact (13) alignment can be achieved using oxidized sidewalls (17) of polycrystalline silicon alignment mesas (14) defined in the same polysilicon as the emitter mesa (7) but deposited on oxide (2) rather than the implanted base region (5).

Abstract: A process for producing a semiconductor device includes depositing a layer of insulator material onto a supporting substrate of the type having a surface which includes a channel region below the surface thereof containing a carrier concentration of a desired conductivity type, removing selected portions of the insulator material to form a substitutional gate on the substrate surface, forming side walls bounding substitutional gate to define an effective masking area in cooperation with the substitutional gate, ion implanting a dopant into the unmasked region of the substrate, removing the side walls, annealing the resultant device, removing the substitutional gate, depositing gate metal and first and second ohmic contacts in correct positional relation to one another on the substrate, and depositing metallic interconnects in electrical communication with the ohmic contacts to produce a semiconductor device.

Abstract: A method of using removable sidewall spacers to minimize the need for mask levels in forming lightly doped drains (LDDs) in the formation of CMOS integrated circuits. Aluminum or chemical vapor deposition (CVD) metals such as tungsten are suitable materials to form removable sidewall spacers which exist around CMOS gates during heavily doped source/drain region implants. Other materials such as CVD polysilicon may also be useful for the sidewall spacers. The sidewall spacers are removed before implantation of the lightly doped drain regions around the gates. This implanation sequence is exactly the reverse of what is currently practiced for lightly doped drain formation. The invention also includes the use of a differential oxide layer. A second set of disposable sidewall spacers or the use of permanent sidewall spacers form optional embodiments.

Abstract: The vapor phase growth on semiconductor wafers is carried out by an apparatus in which a multiplicity of semiconductor wafers are held by a holder so that the semiconductor wafers lie one over another in a vertical direction, and are rotated together with the holder, the holder is placed in a heater disposed in a reaction vessel, a raw material gas supply nozzle and a raw material gas exhaust nozzle are provided within the heater so that the semiconductor wafers are interposed between the gas supply nozzle and the gas discharge nozzle, and the gas supply nozzle and the gas discharge nozzle have gas supply holes and gas discharge holes, respectively, so that a raw material gas can flow on each semiconductor wafer in horizontal directions. When the temperature of the heater is raised by a heating source to heat the semiconductor wafers, the raw material gas is supplied from the gas supply holes to each semiconductor wafer, and thus a uniform layer is grown on each semiconductor wafer from the raw material gas.

Abstract: A method for forming a titanium tungsten fuse begins with the steps of forming a silicon dioxide layer (42), a titanium tungsten layer (44) and a aluminum layer (46) on a silicon substrate (40). The titanium tungsten layer serves as fuse material while the aluminum layer serves as interconnect material. A photolithographic mask (48) is then applied to the wafer. The portion of the aluminum layer exposed by the photolithographic mask and the portion of the titanium tungsten layer lying thereunder are then removed. Because both the aluminum and titanium tungsten layers are etched simultaneously, a dry etching process can be used during this step. The resulting structure includes a thin aluminum and titanium tungsten region where the resulting fuse is to be formed. Thereafter, the first photolithographic mask is removed and a second photolithographic mask is applied to the wafer which includes a window region where the titanium tungsten fuse is to formed.

Abstract: Nitride layers are formed on semiconductor substrates utilizing alkali metals as catalysts. The surface of the semiconductor substrate first has a thin layer of an alkali metal deposited thereon and then is exposed to nitrogen from a nitrogen source at temperatures and pressures sufficient to grow a nitride layer, which will generally occur at lower temperatures than required for nitride formation by conventional processes. The surface is then annealed and the catalyst removed by heating at moderate temperatures, desorbing the catalyst and leaving a nitride layer on the surface of the substrate which is uncontaminated by the alkali metal catalyst. The process is particularly suited to the formation of nitride layers on silicon utilizing essentially a monolayer of the alkali metal such as sodium.

Abstract: A semiconductor laser element includes a first cladding layer of first conductivity type provided on a semiconductor substrate of the first conductivity type; a current blocking layer of a second conductivity type provided on the first cladding layer having a stripe groove from which the first cladding layer and is exposed at the bottom thereof; a light guide layer of the first conductivity type provided covering the current blocking layer, the stripe groove, and the first cladding layer exposed from the groove; an active layer provided on the light guide layer curved in the neighborhood of the stripe groove, whose refractive index is larger than that of the light guide layer; and a second cladding layer of the second conductivity type provided on the active layer, whose refractive index is smaller than that of the active layer.

Abstract: The use of arsenosilicate glass (ASG) as a dielectric layer in semiconductors, and methods of producing arsenosilicate glasses as conformal coatings are described. The ASG coatings may be produced as the result of heterogeneous reactions involving silane, arsine and oxygen. In multilevel semiconductors ASG may be used over the polysilicon gates 3, over aluminum metallization 5 and second dielectric layer 6, and/or over second metallization 7.

Abstract: A first insulative film is formed with predetermined height and thickness in a loop shape on the surface of the Schottky-junction semiconductor substrate. A gate electrode metal film is formed with a predetermined height and thickness in a loop shape on the surface of the substrate along the inner surface of the first insulative film. A second insulative film is formed with a predetermined height and thickness in a loop shape on the surface of the substrate along the inner surface of the metal film. A channel consisting of a low concentration impurity layer, is formed in a loop shape inside the substrate directly under the metal film and the first and second insulative films. The source region consists of a high-concentration impurity layer formed such that it surrounds the channel positioned inside the substrate on the outside of the first insulative film.

Abstract: A 3D epitaxial structure is described in which metal compounds are formed in a semiconductor layer, the metal compounds being epitaxial with the semiconductor layer and having a top surface which is planar with the top surface of the semiconductor layer. Onto this another layer can be epitaxially grown, such as an additional semiconductor layer. The technique for forming such a structure utilizes a starting material for metal compound formation which leaves a residue that is preferentially etched in order to preserve the embedded metal compound and to leave a substantially planar surface comprising the metal compound epitaxial regions and the unreacted surface regions of the semiconductor layer.

Abstract: A method for manufacturing semiconductor device with improved frequency characteristics is provided. The base resistance and the base-to-collector capacitance are reduced by minimizing a base area and a space between an emitter and the base. The minimization of the base area is brought about by forming the emitter region in the base region by self-aligned process. The minimization of the space between the emitter and the base is accomplished by presenting only an insulator layer between a silicon layer on the emitter region and a metal wiring on the base region.

Abstract: A method of manufacturing an insulated gate field effect transistor by forming a non-single crystalline semiconductor film of a first conductivity type on an insulating substrate where the semiconductor film includes hydrogen or fluoride, forming a gate insulating film on part of the semiconductor film to be the gate region, forming a gate electrode on the insulating film, inverting the conductivity type of the part of the conductor film to be the source and grain regions by ion doping of impurity corresponding to the second conductivity type opposite to the first conductivity type with the gate electrode functioning as a mask, and then exposing the non-single-crystalline semiconductor film to illumination with the gate electrode functioning as a mask to selectively crystallize the source and drain regions.

Abstract: This process consists of producing patterns (17) of an insulating material on a monocrystalline silicon substrate (12), depositing on the complete structure an amorphous or polycrystalline silicon film (26), covering the latter with a layer (28) of an encapsulating material, carrying out a heat treatment on the structure obtained serving to vertically embed in substrate (12) the insulating material patterns (17) and forming above the latter a monocrystalline silicon layer (33), eliminating the encapsulating material layer (28) and etching the monocrystalline silicon layer obtained (33), so as to form said islands (34).

Abstract: A method of manufacturing a semiconductor device is set forth including the step of depositing from a vapor phase crystalline layers on a substrate in a chamber of a reactor (R) by means of vector gases and reacting gases. The vector gases and reacting gases are introduced into the chamber of the reactor by means of one or several systems of tubes, each system composed on the one hand of a main tube (P), one end of which merges into the reactor (R) and the other end of which merges at an outlet (E), and on the other hand of three secondary tubes (6,5,7) designated as first (6), second (5) and third (7) secondary tubes with the main tube (P) comprising four restrictions (1,2,3,4) between which the three respective secondary tubes merge. The first secondary tube (6) merges closest to the reactor (R). The first (6) and third (7) secondary tubes serve to transport the vector gas(es) at a flow rate D.sub.1 and D.sub.

Abstract: A wafer process flow encompasses an arbitray repeated layered structure of heteroepitaxial layers of silicon based films with process control throughout the strata of chemical potential and recombination velocity, suitable for both high performance MOS and bipolar transistors with three dimensional transistor capability. A non-compensated doping technique preserves crystalline periodicity, as does the component delineation by means of anisotropic etching. The wafer is hermetic by means of the semi-insulation films polyimide, and the elimination of phosphorous doped silicon dioxide. A metallurgy system enables a high level integration.

Abstract: It has been found that through the use of ferrocene or iron pentacarbonyl based compounds, it is possible to produce semi-insulating epitaxial layers of indium phosphide-based compounds by an MOCVD process. Resistivities up to 1.times.10.sup.9 ohm-cm have been achieved as compared to resistivities on the order of 5.times.10.sup.3 ohm-cm for other types of semi-insulating epitaxial indium phosphide.