Abstract: In a semiconductor device having a thin insulating film of 300 .ANG. or less in thickness on which a conductive layer is provided, the conductive layer is connected to the semiconductor substrate at a position outside the active regions. With such a structure, negative charges accumulated on the conductive layer during the reactive ion etching or ion implantation process can be easily discharged to the semiconductor substrate to prevent a dielectric breakdown of the thin insulating film. In the embodiment, the thin insulating film is a dielectric film of a MOS storage capacitor of a one-transistor type memory cell and the conductive layer is the upper electrode of the MOS capacitor.

Abstract: A highly planarized integrated circuit structure having at least one bipolar device and at least one MOS device is described as well as a method of making the structure. The structure comprises a substrate having a field oxide grown thereon with portions defined therein respectively for formation of a collector region and a base/emitter region for a bipolar device and a source/gate/drain region for an MOS device. All of the contacts of the devices are formed using polysilicon which fills the defined portions in the field oxide resulting in the highly planarized structure.

Abstract: A lateral bipolar transistor is described incorporating at least two grooves extending from the upper surface and spaced apart by a predetermined amount from which impurities are introduced to form an emitter region extending from the sidewall of one groove and a collector region extending from the sidewall of an adjacent groove with the base being the substrate material between the two regions. A plurality of grooves may be utilized to form a plurality of transistors with the grooves staggered to facilitate access to the ends of the grooves functioning as emitters and those functioning as collectors. The large vertical junction area formed by the side walls relative to the horizontal junction area at the bottom of the grooves and the uniform base width result in a high current gain lateral transistor.

Abstract: The problem of unwanted residual polysilicon stringers along the sidewalls of a field oxide layer employed in direct moat wafer processing is avoided by a processing scheme in which the sidewalls of the aperture in the field oxide layer are initially tapered prior to formation of the polysilicon layer to be used for the gate electrode(s). Because of the graduated thickness of the sidewalls of the field oxide layer, the thickness of the polysilicon layer formed thereon is substantially uniform over the entirety of the substrate. As a result, during subsequent masking of the polysilicon layer to define the gate electrode(s), all unmasked portions of the polysilicon are completely etched, leaving no residual material (e.g. stringers) that could be a source of device contamination.

Abstract: The invention discloses an improved process for forming one or more metal strips on an integrated circuit structure by wet etching of a metal layer which comprises forming an intermediate layer over the integrated circuit structure; forming slots in the intermediate layer; forming a metal layer over the intermediate layer; and wet etching the metal layer sufficiently to remove all metal in the slots while retaining metal on the intermediate layer between the slots to form the desired one or more metal strips. Multiple levels of metal strips may be formed in an integrated circuit structure using the method of the invention.

Abstract: A semiconductor device comprises a semiconductor substrate, an active region positioned in a portion of the substrate and a field insulating layer surrounding the active region and partially embedded in the substrate. The semiconductor device according to the present invention further comprises an insulating member positioned under and attached to the bottom of the field insulating layer and surrounding the active region with the field insulating layer. Because of this insulating member, the thickness of the field insulating layer can be reduced to a small value. Therefore, a PN junction formed in the active region can be terminated at the insulating member without any sharp curvature, that is, the PN junction can extend flatly. Further, silicon crystal near the field insulating layer has only a small amount of defects or no defect so that any abnormal diffusion of impurity near the field insulating layer can be prevented.

Abstract: A highly planarized integrated circuit structure having at least one MOS device is described as well as a method of making the structure. The structure comprises a substrate having a field oxide grown thereon with at least one portion defined therein for formation of a source/gate/drain region for an MOS device. All of the contacts of the device are formed using polysilicon which fills the defined portions in the field oxide resulting in the highly planarized structure.

Abstract: A method of growing an epitaxial doped chromium buffer layer is described. A first flow of arsenic trichloride and hydrogen is directed through a retort having disposed therein at an elevated temperature chromium and gallium arsenide crystals. The arsenic trichloride reacts with the chromium and the gallium arsenic crystals to produce chromium chloride, gallium chloride and arsenic. This vapor stream is then directed into a reactor tube where a second flow of gallium chloride and arsenic is provided. Deposited from these flows is gallium arsenide doped with chromium.

Abstract: A highly planarized integrated circuit structure having at least one bipolar device is described as well as a method of making the structure. The structure comprises a substrate having a field oxide grown thereon with openings defined therein respectively for formation of a collector contact region and a base/emitter region for a bipolar device in the substrate. All of the contacts of the bipolar device are formed using polysilicon which fills the defined openings in the field oxide resulting in a highly planarized structure.

Abstract: A three-dimensional CMOS integrated circuit structure in which two complementary field effect transistors are fabricated in vertical alignment with one another, and in which both transistors are single crystal and share a common crystal lattice structure and form a single unitary crystalline structure.

Abstract: A plurality of monocrystalline silicon seeds is disposed on an insulator layer which is disposed on a substantially flat major surface of a silicon wafer. A first monocrystalline silicon deposit of first conductivity type is formed on a first silicon seed and a second monocrystalline silicon deposit, of similar configuration, is formed on a second silicon seed. The first and second deposits are then covered with insulator layers and a third monocrystalline deposit is formed on a third silicon seed. The third deposit has a top surface height substantially equal to or less than that of the top surfaces of the first and second deposits. An insulator layer is then formed on the top surface of the third deposit and first and second monocrystalline islands are formed on this insulator layer. Complementary bipolar transistors are formed in the first and second monocrystalline silicon deposits and PMOS and NMOS transistors are formed in the first and second islands on the third insulator layer.

Abstract: A process for fabricating a self-aligned three-dimensionally integrated circuit structure having two channel regions responsive to a common gate electrode. A relatively thick lift-off region is formed over and in alignment with the gate electrode. A thick oxide layer is then deposited over the structure so as to form stressed oxide extending from the lift-off layer sidewalls. A selective etch of the stressed oxide follows. The relatively thick oxide covering the lift-off layer is then removed with the etch of the lift-off layer, the lift-off etch acting through the exposed lift-off layer sidewalls. The formation of an upper field effect transistor gate oxide and a conformal deposition of polysilicon for the channel and source/drain regions follows. The conformally deposited polysilicon retains the contour of the recess formed by the lift-off.

Abstract: Disclosed is a method for forming a conductor pattern which comprises the steps of forming a conductive layer on a semiconductor substrate, forming a photoresist film on the conductive layer, removing that portion of the photoresist film located on a conductor pattern forming region of the conductive layer, forming a first masking metal film over the whole surface of the resultant structure, removing the photoresist film along with that portion of the first masking metal film formed thereon so that a portion of the first masking film remains on the conductor pattern forming region of the conductive layer to form a first masking metal pattern, and selectively removing the conductive layer by anisotropic etching to form the conductor pattern.Since the selective removal of the conductor layer is accomplished by the use of the metal pattern as a mask, it is possible to form a much finer conductor pattern than is obtained with the use of the photoresist pattern as the mask.